10 Aug, 2013
13 commits
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B4860 and B4420 has PCIe version 2.4 IP instead of 3.x
Signed-off-by: Roy Zang
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T4240 PCIe IP is version 3.0 and has some update comparing previous
QorIQ products.1. Move Freescale specific register define
to
arch/powerpc/include/asm/fsl_pci.h
and update the register offset define for T4240.2. add the status/control register define
use status/control register to judge the link status3. The original code uses 'Programming Interface' field to judge if PCIE is
EP or RC mode, however, T4240 does not support this functionality.
According to PCIE specification, 'Header Type' offset 0x0e is used to
indicate header type, so for PCIE controller, the patch changes code to
use 'Header Type' field to identify if the PCIE is RC or EP mode.This patch fixes the PCIe card link up issue on T4240QDS.
Signed-off-by: Roy Zang
Signed-off-by: Minghuan Lian
Signed-off-by: York Sun -
It allows files not in the same path to use this function
as required by B4 board fileSigned-off-by: Shaveta Leekha
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Also change the define name SRDS_RSTCTL_SDPD to
SRDS_RSTCTL_SDEN, which stands for SerDes enable
as mentioned in SerDes module guideSigned-off-by: Shaveta Leekha
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BSC9132 SoC has two separate DDR controllers for PowerPC side and DSP side
DDR. They are mapped to PowerPC and DSP CCSR space respectively.
BSC9132QDS has two on-board MC34716EP DDR3 memory one connected to PowerPC
and other to DSP side controller.Configure DSP DDR controller similar to PowerPC side DDR controller as
memories are exactly similar.Signed-off-by: Manish Jaggi
Signed-off-by: Priyanka Jain
Acked-by: York Sun -
BSC9132QDS is a Freescale Reference Design Board for BSC9132 SoC which is a
integrated device that contains two powerpc e500v2 cores and two DSP
starcores.To support DSP starcore
-Creating LAW and TLB for DSP-CCSR space.
-Creating LAW for DSP-core subsystem M2 and M3 memory
-Creating LAW for 1GB DDR which is connected exclusively to DSP-coresSigned-off-by: Manish Jaggi
Signed-off-by: Priyanka Jain
Acked-by: York Sun -
Erratum A-005812 Incorrect reservation clearing in Write Shadow mode can
result in invalid atomic operations. For u-boot, this erratum only impacts
SoCs running in write shadow mode.Signed-off-by: York Sun
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JEDEC spec requires the clocks to be stable before deasserting reset
signal for RDIMMs. Clocks start when any chip select is enabled and
clock control register is set. This patch also adds the interface to
toggle memory reset signal if needed by the boards.Signed-off-by: York Sun
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On selected platforms, x4 DDR devices can be supported. Using x4 devices may
lower the performance, but generally they are available for higher density.Tested on MT36JSF2G72PZ-1G9E1 RDIMM.
Signed-off-by: York Sun
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Move CONFIG_FSL_CORENET define to config_mpc85xx.h. It is not board
specific feature and belongs to SoC header.Signed-off-by: York Sun
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For T4 platform, the SRIO LIODN registers are in SRIO address space
and not in GUTs.Signed-off-by: Liu Gang
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For B4, the SRIO LIODN registers are in SRIO address space and not
in GUTs.Signed-off-by: Liu Gang
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For some PowerPC platforms, LIODN registers for SRIO ports are
in SRIO register address space. So the ccsr_rio structure should
be updated for those LIODN registers.In addition, add a new macro "SET_SRIO_LIODN_BASE" to create
the SRIO LIODN ID table based on the SRIO LIODN register address.Signed-off-by: Liu Gang
Acked-by: York Sun
24 Jul, 2013
2 commits
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The sandburst-specific i2c drivers have been deleted, conflict was just
over the SPDX conversion.Conflicts:
board/sandburst/common/ppc440gx_i2c.c
board/sandburst/common/ppc440gx_i2c.hSigned-off-by: Tom Rini
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Signed-off-by: Wolfgang Denk
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini
23 Jul, 2013
1 commit
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Signed-off-by: Dirk Eibach
Cc: Heiko Schocher
Cc: Stefan Roese
Tested-by: Stefan Roese
21 Jun, 2013
8 commits
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Erratum A-006593 is "Atomic store may report failure but still allow
the store data to be visible".The workaround is: "Set CoreNet Platform Cache register CPCHDBCR0 bit
21 to 1'b1. This may have a small impact on synthetic write bandwidth
benchmarks but should have a negligible impact on real code."Signed-off-by: Scott Wood
Signed-off-by: Andy Fleming -
Calculate reserved fields according to IFC bank count
1. Move csor_ext register behind csor register and fix res offset
2. Move ifc bank count to config_mpc85xx.h to support 8 bank count
3. Guard fsl_ifc.h with CONFIG_FSL_IFC macro to eliminate the compile
error on some devices that does not have IFC controller.Signed-off-by: Mingkai Hu
Signed-off-by: Andy Fleming -
When a T4 board boots from SRIO or PCIE, it needs to finish these processes:
1. Set all the cores in holdoff status.
2. Set the boot location to one PCIE or SRIO interface by RCW.
3. Set a specific TLB entry for the boot process.
4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot.
5. Set a specific TLB entry in order to fetch ucode and ENV from
master.
6. Set a LAW entry with the TargetID one of the PCIE ports for
ucode and ENV.
7. Slave's u-boot image should be generated specifically by
make xxxx_SRIO_PCIE_BOOT_config.
This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.For more information about the feature of Boot from SRIO/PCIE, please
refer to the document doc/README.srio-pcie-boot-corenet.Signed-off-by: Liu Gang
Signed-off-by: Andy Fleming -
When a b4860qds board boots from SRIO or PCIE, it needs to finish these
processes:
1. Set all the cores in holdoff status.
2. Set the boot location to one PCIE or SRIO interface by RCW.
3. Set a specific TLB entry for the boot process.
4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot.
5. Set a specific TLB entry in order to fetch ucode and ENV from
master.
6. Set a LAW entry with the TargetID one of the PCIE ports for
ucode and ENV.
7. Slave's u-boot image should be generated specifically by
make xxxx_SRIO_PCIE_BOOT_config.
This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.For more information about the feature of Boot from SRIO/PCIE, please
refer to the document doc/README.srio-pcie-boot-corenet.Signed-off-by: Liu Gang
Signed-off-by: Andy Fleming -
Currently, the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" can enable
the master module of Boot from SRIO and PCIE on a platform. But this
is not a silicon feature, it's just a specific booting mode based on
the SRIO and PCIE interfaces. So it's inappropriate to put the macro
into the file arch/powerpc/include/asm/config_mpc85xx.h.Change the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" to
"CONFIG_SRIO_PCIE_BOOT_MASTER", remove them from
arch/powerpc/include/asm/config_mpc85xx.h file, and add those macros
in configuration header file of each board which can support the
master module of Boot from SRIO and PCIE.Signed-off-by: Liu Gang
Signed-off-by: Andy Fleming -
All the other constants use lowercase 'x' in "MPC85xx", so we
duplicate that here.Signed-off-by: Andy Fleming
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BSC9132 has 3 IFC banks.
Signed-off-by: York Sun
Signed-off-by: Andy Fleming -
BSC9131RDB is a Freescale Reference Design Board for
BSC9131 SoC which is a integrated device that contains
one powerpc e500v2 core and one DSP starcore.To support DSP starcore
-Creating LAW and TLB for DSP-CCSR space.
-Creating LAW for DSP-core subsystem M2 memorySigned-off-by: Priyanka Jain
Signed-off-by: Poonam Aggrwal
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Andy Fleming
12 Jun, 2013
1 commit
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C99's strict aliasing rules are insane to use in low-level code such as a
bootloader, but as Wolfgang has rejected -fno-strict-aliasing in the
past, add a union so that 16-bit accesses can be performed.Compile-tested only.
Signed-off-by: Scott Wood
Acked-by: Wolfgang Denk
30 May, 2013
1 commit
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Conflicts:
common/cmd_fpga.c
drivers/usb/host/ohci-at91.c
25 May, 2013
7 commits
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Boot ROM code creates TLB entries for 3.5G space before entering
the u-boot. Earlier we were deleting these entries after early
initialization of CPU. In recent past, code has been added
to invalidate all these entries before relocation of u-boot code.
So this code to delete TLB entries after CPU initialization
is no longer required.Signed-off-by: Ruchika Gupta
Acked-by: Matthew McClintock
Signed-off-by: Andy Fleming -
Signed-off-by: Shaveta Leekha
Signed-off-by: Andy Fleming -
B4420 is a subset of B4860. Merge them in config_mpc85xx.h to simplify
the defines.
- Removed #define CONFIG_SYS_FSL_NUM_CLUSTERS as this is used nowhere.
- defined CONFIG_SYS_NUM_FM1_10GEC to 0 for B4420 as it does not have 10G.Also move CONFIG_E6500 out of B4860QDSds.h into config_mpc85xx.h.
Signed-off-by: Poonam Aggrwal
Signed-off-by: Andy Fleming -
To align with chassis generation 2 spec, all cores are numbered in sequence.
The cores may reside across multiple clusters. Each cluster has zero to four
cores. The first available core is numbered as core 0. The second available
core is numbered as core 1 and so on.Core clocks are generated by each clusters. To identify the cluster of each
core, topology registers are examined.Cluster clock registers are reorganized to be easily indexed.
Signed-off-by: York Sun
Signed-off-by: Andy Fleming -
T1040 and variants have e5500 cores and are compliant to QorIQ Chassis
Generation 2. The major difference between T1040 and its variants is the
number of cores and the number of L2 switch ports.Signed-off-by: York Sun
Signed-off-by: Andy Fleming -
T4160 is a subset of T4240. Merge them in config_mpc85xx.h to simplify
the defines. Also move CONFIG_E6500 out of t4qds.h into config_mpc85xx.h.Signed-off-by: York Sun
Signed-off-by: Andy Fleming -
This is compile-time config.
Signed-off-by: James Yang
Signed-off-by: Andy Fleming
15 May, 2013
7 commits
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The Freescale MPC8220 Power Architecture processors have long reached
EOL; Freescale does not even list these any more on their web site.Remove the code to avoid wasting maitaining efforts on dead stuff.
Signed-off-by: Wolfgang Denk
Cc: Andy Fleming -
Removed unused declare serdes_get_prtcl() which was no longer needed.
Signed-off-by: Shengzhou Liu
Signed-off-by: Andy Fleming -
1, Implemented board_ft_fman_fixup_port() to fix port for kernel.
2, Implemented fdt_fixup_board_enet() to fix node status of different
slots and interfaces.
3, Adding detection of slot present for XGMII interface.
4, There is no PHY for XFI, so removed related phy address settings.Signed-off-by: Shengzhou Liu
Signed-off-by: Andy Fleming -
T4160 SoC is low power version of T4240. The T4160 combines eight dual
threaded Power Architecture e6500 cores and two memory complexes (CoreNet
platform cache and DDR3 memory controller) with the same high-performance
datapath acceleration, networking, and peripheral bus interfaces.Signed-off-by: York Sun
Signed-off-by: Andy Fleming -
T4240 internal UTMI phy is different comparing to previous UTMI PHY
in P3041.
This patch adds USB 2.0 UTMI Dual PHY new memory map and enable it for
T4240.
The phy timing is very sensitive and moving the phy enable code to
cpu_init.c will not work.Signed-off-by: Roy Zang
Signed-off-by: Andy Fleming -
Fix ccsr_gur for corenet platform. Remove non-exist registers. Add fuse
status register.Signed-off-by: York Sun
Signed-off-by: Andy Fleming
