18 May, 2013
3 commits
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Signed-off-by: Masahiro Yamada
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It appears that there are some cases where we have more than 4 banks
of memory. Use CONFIG_NR_DRAM_BANKS if it's defined to handle this.
This will take up a little extra stack space (64 bytes extra if we go
up to 8 banks), but that seems OK.Signed-off-by: Doug Anderson
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This makes fixup_silent_linux() use malloc() to allocate its
working space, meaning that our maximum kernel command line
should only be limited by malloc(). Previously it was silently
overflowing the stack.Note that nothing about this change increases the kernel's maximum
command line length. If you have a command line that is >256
bytes it's up to you to make sure that kernel can handle it.Signed-off-by: Doug Anderson
Acked-by: Mike Frysinger
16 May, 2013
3 commits
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Signed-off-by: Tom Rini
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The logic for the whether to configure for polling or DMA
was mistakenly reversed in this patch:Commit 7b43db92110ec2f15c5f7187a165f2928464966b
drivers/mmc/fsl_esdhc.c: fix compiler warningsSigned-off-by: Haijun Zhang
CC: Sun Yusong-R58495
Signed-off-by: Andy Fleming -
Faraday FTSDC010 is a MMC/SD host controller.
Although there is already a driver in current u-boot release,
which is modified from eSHDC and contributed by Andes Tech.
Its performance is too terrible on Faraday A36x SoC platforms,
so I turn to implement this new version of driver which is
10+ times faster than the old one.It's carefully designed to be compatible with Andes chips,
so it should be safe to replace it.Signed-off-by: Kuo-Jung Su
CC: Andy Fleming
Signed-off-by: Andy Fleming
15 May, 2013
34 commits
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The Freescale MPC8220 Power Architecture processors have long reached
EOL; Freescale does not even list these any more on their web site.Remove the code to avoid wasting maitaining efforts on dead stuff.
Signed-off-by: Wolfgang Denk
Cc: Andy Fleming -
Signed-off-by: Wolfgang Denk
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The mpc85xx repuires a special layout on the memory device that is
connected to the eSDHC controller interface. But the file spl_mmc.c
didn't handle this specfic case, there needs a special treatmen, in
the powerpc drictory. So, there is no longer to keep spl_mmc.c on
mpc85xx, CONFIG_SPL_FRAMEWORK is not set.When CONFIG_SPL_MMC_SUPPORT is set and CONFIG_SPL_FRAMEWORK is not
set, there was an error in drivers/mmc/spl_mmc.c:drivers/mmc/libmmc.o:(.got2+0x8): undefined reference to `spl_image'.
Now, the solution is to move the file "spl_mmc.c" to directory "common/spl".
Signed-off-by: Ying Zhang
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If timeout is occurred at the while loop above,
the value of 'timeout' is -1, not 0.Signed-off-by: Masahiro Yamada
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Signed-off-by: "Paul B. Henson"
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QSGMII card assumed to be used by default, but if SGMII card is used,
it will use different PHY address, but we don't know which card is used
until we access PHY on the card. So we check the card type slot by slot,
if we can read a PHY ID by reading a SGMII PHY address on a slot, then
the slot must have a SGMII card pluged, we mark all ports on that slot,
and fix dts to use the SGMII card PHY address when doing dts fixup
for the marked ports.Signed-off-by: Shaohui Xie
Signed-off-by: Andy Fleming -
Only clear IRE bit in qixis brdcfg5 register and keep other bits
unchanged.Signed-off-by: Ed Swarthout
Signed-off-by: York Sun
Signed-off-by: Andy Fleming -
B4860QDS requires DDRC2 has 0 as base address and DDRC1 has higher address.
This is the requirement for DSP cores to run in 32-bit address space.Signed-off-by: York Sun
Signed-off-by: Andy Fleming -
This gives boards flexibility to assign other than default addresses to each
DDR controller. For example, DDR controler 2 can have 0 as the base and DDR
controller 1 has higher memory.Signed-off-by: York Sun
Signed-off-by: Andy Fleming -
The workaround has been updated to use a slightly different magic number.
Change from 0x00003000 to 0x30003000.Signed-off-by: York Sun
Signed-off-by: Andy Fleming -
This is what we have done for the UTMI PHY on P3041/P5020. Then the PHY
initialization can be reused in kernel without “usb start” command.Signed-off-by: Roy Zang
Signed-off-by: Andy Fleming -
Use QSGMII card PHY address as default SGMII card PHY address, QSGMII card
PHY address is variable depends on different slot.Signed-off-by: Shaohui Xie
Signed-off-by: Andy Fleming -
The VSC8574 is a quad-port Gigabit Ethernet transceiver with four SerDes
interfaces for quad-port dual media capability. This driver supports SGMII
and QSGMII MAC mode. For now SGMII mode is tested.Signed-off-by: Roy Zang
Signed-off-by: Shaohui Xie
Signed-off-by: Andy Fleming -
Removed unused declare serdes_get_prtcl() which was no longer needed.
Signed-off-by: Shengzhou Liu
Signed-off-by: Andy Fleming -
- set proper compatible property name for mEMAC.
- fixed ft_fixup_port for dual-role mEMAC, which will lead to
MAC node disabled incorrectly.Signed-off-by: Shengzhou Liu
Signed-off-by: Andy Fleming -
1, Implemented board_ft_fman_fixup_port() to fix port for kernel.
2, Implemented fdt_fixup_board_enet() to fix node status of different
slots and interfaces.
3, Adding detection of slot present for XGMII interface.
4, There is no PHY for XFI, so removed related phy address settings.Signed-off-by: Shengzhou Liu
Signed-off-by: Andy Fleming -
When CONFIG_SYS_FSL_QORIQ_CHASSIS2 is not defined, QMAN frequency will not
be initialized, and QMAN will have a wrong frequency display.Signed-off-by: Shaohui Xie
Signed-off-by: Andy Fleming -
T4160QDS shares the same platform as T4240QDS. T4160 is a low power
version of T4240, with eight e6500 cores, two DDR3 controllers, and
slightly different SerDes protocols.Signed-off-by: York Sun
Signed-off-by: Andy Fleming -
Separate CONFIG_PPC_T4240 from board config file. Prepare to add more SoC
variants supported on the same board.Signed-off-by: York Sun
Signed-off-by: Andy Fleming -
T4160 SoC is low power version of T4240. The T4160 combines eight dual
threaded Power Architecture e6500 cores and two memory complexes (CoreNet
platform cache and DDR3 memory controller) with the same high-performance
datapath acceleration, networking, and peripheral bus interfaces.Signed-off-by: York Sun
Signed-off-by: Andy Fleming -
Protocols are constants. Fix arrays with const prefix.
Signed-off-by: York Sun
Signed-off-by: Andy Fleming -
The PIR parsing algorithm we used is not only for E6500. It applies to all
SoCs with chassis 2.Signed-off-by: York Sun
Signed-off-by: Andy Fleming -
Use decimal and hexadecimal for protocol numbers. It helps to match with
SoC user manual.Signed-off-by: York Sun
Signed-off-by: Andy Fleming -
T4240 internal UTMI phy is different comparing to previous UTMI PHY
in P3041.
This patch adds USB 2.0 UTMI Dual PHY new memory map and enable it for
T4240.
The phy timing is very sensitive and moving the phy enable code to
cpu_init.c will not work.Signed-off-by: Roy Zang
Signed-off-by: Andy Fleming -
T4240 has voltage ID fuse. Read the fuse and configure the voltage
correctly. Core voltage has higher tolerance on over side than below.Signed-off-by: York Sun
Signed-off-by: Andy Fleming -
Missing nodes of crypto, pme, etc in device tree is not a fatal error.
Setting up the qman portal should skip the missing node and continue
to finish the rest.Signed-off-by: York Sun
Signed-off-by: Andy Fleming -
Should check if interleaving is enabled before using interleaving mode.
Signed-off-by: York Sun
Signed-off-by: Andy Fleming -
Update the timing table to support more rank density, based on the theory
that similar density DIMMs have similar clock adjust and write level start
timing. Update the timing for 1600 and 1866 MT/s. Tested with Micron
MT18JSF1G72AZ-1G9E1 DIMMs, iDIMM M3CN-4GMJ3C0C-M92.Signed-off-by: York Sun
Signed-off-by: Andy Fleming -
Lane H on SerDes4 should be SATA2 instead of SATA1
Signed-off-by: Jerry Huang
Signed-off-by: Roy Zang
Signed-off-by: Andy Fleming -
1. fix 10G mac offset by plus 8;
2. add second 10G port info for FM1 & FM2 when init ethernet info;
3. fix 10G lanes name to match lane protocol table;Signed-off-by: Shaohui Xie
Signed-off-by: Roy Zang
Signed-off-by: Andy Fleming -
Signed-off-by: Shaohui Xie
Signed-off-by: Roy Zang
Signed-off-by: Andy Fleming -
Reverse the bit sequence to set and display serdes clock frequency
correctly. The correct bit maps in BRDCFG2 are
0 1 2 3 4 5 6 7
S1RATE[1:0] S2RATE[1:0] S3RATE[1:0] S4RATE[1:0]Signed-off-by: Roy Zang
Signed-off-by: Andy Fleming -
The L1 D-cache on e6500 is write-through. This means that it's not
considered a good idea to have the L1 up and running if the L2 is
disabled. We don't actually *use* the L1 until after the L2 is
brought up on e6500, so go ahead and move the L1 enablement after
that code is done.Signed-off-by: Andy Fleming
