Eric Lee / smarc-uboot

07 May, 2018

1 commit

  • 83d290c56   SPDX: Convert all of our single license tags to Linux Kernel style ... Browse Code »
    60

    When U-Boot started using SPDX tags we were among the early adopters and
    there weren't a lot of other examples to borrow from. So we picked the
    area of the file that usually had a full license text and replaced it
    with an appropriate SPDX-License-Identifier: entry. Since then, the
    Linux Kernel has adopted SPDX tags and they place it as the very first
    line in a file (except where shebangs are used, then it's second line)
    and with slightly different comment styles than us.

    In part due to community overlap, in part due to better tag visibility
    and in part for other minor reasons, switch over to that style.

    This commit changes all instances where we have a single declared
    license in the tag as both the before and after are identical in tag
    contents. There's also a few places where I found we did not have a tag
    and have introduced one.

    Signed-off-by: Tom Rini

    Tom Rini
     

07 Sep, 2016

1 commit

  • 154469881   ARM: armv7: move ARMV7_PSCI_NR_CPUS to Kconfig ... Browse Code »
    30

    Move this option to Kconfig and set its default value to 4; this
    increases the number of supported CPUs for some boards.

    It consumes 1KB memory per CPU for PSCI stack, but it should not
    be a big deal, given the amount of memory used for the modern OSes.

    Reviewed-by: Alexander Graf
    Signed-off-by: Masahiro Yamada

    Masahiro Yamada
     

16 Jul, 2016

1 commit

27 May, 2016

1 commit

  • 0dac6b4e8   net: Move the VCI and client arch values to Kconfig ... Browse Code »

    We have a bunch of boards that define their vendor class identifier and
    client archs in the board files or in the distro config. Move everything
    to the generic Kconfig options.

    We're missing the distinction between i386 and x86_64, as I couldn't find
    any config variable that would tell us the difference. Is that really important
    to people? I guess not, so I left it out.

    Signed-off-by: Alexander Graf
    Reviewed-by: Tom Rini

    Alexander Graf
     

06 Feb, 2016

1 commit

  • a187559e3   Use correct spelling of "U-Boot" ... Browse Code »

    Correct spelling of "U-Boot" shall be used in all written text
    (documentation, comments in source files etc.).

    Signed-off-by: Bin Meng
    Reviewed-by: Heiko Schocher
    Reviewed-by: Simon Glass
    Reviewed-by: Minkyu Kang

    Bin Meng
     

13 Aug, 2015

1 commit

24 Nov, 2014

1 commit

15 Oct, 2013

1 commit

04 Oct, 2013

2 commits

  • e261c83aa   ARM: VExpress: enable ARMv7 virt support for VExpress A15 ... Browse Code »

    To enable hypervisors utilizing the ARMv7 virtualization extension
    on the Versatile Express board with the A15 core tile, we add the
    required configuration variable.
    Also we define the board specific smp_set_cpu_boot_addr() function to
    set the start address for secondary cores in the VExpress specific
    manner.
    There is no need to provide a custom smp_waitloop() function here.

    This also serves as an example for what to do when adding support for
    new boards.

    Signed-off-by: Andre Przywara

    Andre Przywara
     
  • 16212b594   ARM: add assembly routine to switch to non-secure state ... Browse Code »

    While actually switching to non-secure state is one thing, another
    part of this process is to make sure that we still have full access
    to the interrupt controller (GIC).
    The GIC is fully aware of secure vs. non-secure state, some
    registers are banked, others may be configured to be accessible from
    secure state only.
    To be as generic as possible, we get the GIC memory mapped address
    based on the PERIPHBASE value in the CBAR register. Since this
    register is not architecturally defined, we check the MIDR before to
    be from an A15 or A7.
    For CPUs not having the CBAR or boards with wrong information herein
    we allow providing the base address as a configuration variable.

    Now that we know the GIC address, we:
    a) allow private interrupts to be delivered to the core
    (GICD_IGROUPR0 = 0xFFFFFFFF)
    b) enable the CPU interface (GICC_CTLR[0] = 1)
    c) set the priority filter to allow non-secure interrupts
    (GICC_PMR = 0xFF)

    Also we allow access to all coprocessor interfaces from non-secure
    state by writing the appropriate bits in the NSACR register.

    The generic timer base frequency register is only accessible from
    secure state, so we have to program it now. Actually this should be
    done from primary firmware before, but some boards seems to omit
    this, so if needed we do this here with a board specific value.
    The Versatile Express board does not need this, so we remove the
    frequency from the configuration file here.

    After having switched to non-secure state, we also enable the
    non-secure GIC CPU interface, since this register is banked.

    Since we need to call this routine also directly from the smp_pen
    later (where we don't have any stack), we can only use caller saved
    registers r0-r3 and r12 to not mess with the compiler.

    Signed-off-by: Andre Przywara

    Andre Przywara
     

24 Jul, 2013

1 commit

23 May, 2013

1 commit