21 Sep, 2018

2 commits

  • camera sometime can't been open once run M4 image.
    ISI-CH0 probe funtion is not called when meet issue.

    The root cause is:
    M4 image set assign resource SC_R_ISI_CH0 into m4 partition
    when open camera in m4 side.
    Uboot will call update_fdt_with_owned_resources to check the pd
    in current dts node. it will call sc_rm_is_resource_owned to
    check the pd whether in other partition, If yes, it will delete
    the dts node. uboot delete isi_0 node whose pd is SC_R_ISI_CH0.

    Change-Id: I4e2afbed2c55caad0a9f804fa8d85511c3bfea38
    Signed-off-by: zhang sanshan

    zhang sanshan
     
  • The "imx_env.h" is not included, so when using default mfgtool environments,
    we get build break.

    Signed-off-by: Ye Li
    Reviewed-by: Peng Fan

    Ye Li
     

20 Sep, 2018

3 commits

  • Since we set the fdt_file value when running on iMX6ULZ. This
    cause the saved fdt_file change be overwritten. So users can't
    set to their own fdt_file.

    Signed-off-by: Ye Li
    Reviewed-by: Peng Fan

    Ye Li
     
  • Since the mx6ulz don't have FEC, it needs to use USB2NET dongle
    to connect network. We decouple the CONFIG_FEC_MXC with CONFIG_CMD_NET.
    For 6ull, all defconfigs need to enable the CONFIG_FEC_MXC explicitly.

    Another change is adding ${usb_net_cmd} environment for usb start command
    in netboot scripts on 6ulz.

    Signed-off-by: Ye Li
    Reviewed-by: Peng Fan

    Ye Li
     
  • When running uuu on iMX8MQ, meet USB enumeration failure in fastboot.
    The root cause is a cache issue in dwc3 driver. When the issue happens, the ctrl_req in
    gadget driver is allocated at 0xfe932f40, and the usb_composite_dev (cdev)
    is allocated at 0xfe932f60. So after we submit the setup request (cache flushed) to USB
    controller, any accessing to usb_composite_dev variable will cause the cache refill, then
    when setup transfer is completed, reading the setup data in ctrl_req will gets old value from
    cache not from memory.

    The ctrl_req is allocated by API dma_alloc_coherent, but u-boot don't have cohernet memory.
    so it still needs cache maintain operations before/after HW accessing. Since the cache flush or
    invalidate bases on cache line, so when the allocated memory size is not cache line aligned,
    potentially it may meet such issue.

    This patch modifies the dma_alloc_coherent API to round the size to cache line aligned.

    Signed-off-by: Ye Li
    Reviewed-by: Peng Fan

    Ye Li
     

18 Sep, 2018

5 commits


17 Sep, 2018

1 commit


15 Sep, 2018

2 commits


14 Sep, 2018

3 commits


13 Sep, 2018

6 commits


12 Sep, 2018

16 commits


11 Sep, 2018

2 commits