06 May, 2014
2 commits
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Add missing header.
Warnings:
drivers/net/zynq_gem.c:491:5: warning: symbol 'zynq_gem_initialize' was not declared. Should it be static?
drivers/net/zynq_gem.c:542:5: warning: symbol 'zynq_gem_of_init' was not declared. Should it be static?Signed-off-by: Michal Simek
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MII is used by this driver.
Signed-off-by: Michal Simek
29 Apr, 2014
2 commits
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Most of the I2C slaves support accesses in the typical style
that is : read/write series of bytes at particular address offset.
These transactions look like:"
(1) START:Address:Tx:Offset:RESTART:Address[0..4]:Tx/Rx:data[0..n]:STOP"However there are certain devices which support accesses in
terms of the transactions as follows:
(2) "START:Address:Tx:Txdata[0..n1]:Clock_stretching:
RESTART:Address:Rx:data[0..n2]"
Here Txdata is typically a command and some associated data,
similarly Rxdata could be command status plus some data received
as a response to the command sent.Type (1) transactions are currently supportd in the
i2c driver using i2c_read and i2c_write APIs. I2C EEPROMs,
RTC, etc fall in this category.To handle type (2) along with type (1) transactions,
i2c_read() function has been modified.Signed-off-by: Shaveta Leekha
Signed-off-by: Poonam Aggrwal -
This driver needs a data structure in SRAM before SDRAM is available.
This is not alway the case using .data section. Moving this data
structure to global_data guarantees it is writable.Signed-off-by: York Sun
CC: Troy Kisky
26 Apr, 2014
1 commit
23 Apr, 2014
16 commits
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ar8031 has the same config steps with ar8021, so change its
config func to ar8021_config instead of genphy_config.Signed-off-by: Zhao Qiang
Reviewed-by: York Sun -
Add support of loading image, binary for MMC and SPI during SPL boot.
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
SPI driver perform its operation(read/write) on 64KB buffer chunk for data
greater than 64KB. This buffer chunk is allocated from system heap.During SPL boot, 768KB of data is read from SPI flash.
Here, heap size may not be sufficient enough to full-fill 64KB buffer
requirement of SPI driver. So break down u-boot read operation at 8KB of chunk.Also, fix a warning i.e. "unused variable buf" during CONFIG_FSL_CORENET
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
nand_spl_load_image() can also be used for non TPL framework.
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
When T104x soc wakes up from deep sleep, control is passed to the
primary core that starts executing uboot. After re-initialized some
IP blocks, like DDRC, kernel will take responsibility to continue
to restore environment it leaves before.Signed-off-by: Tang Yuantian
Reviewed-by: York Sun -
This is a theoretical possible out of bounds error in DDR driver. Adding
check before using array index. Also change some runtime conditions to
pre-compiling conditions.Signed-off-by: York Sun
Reviewed-by: York Sun -
MDIO clock needs to be initialized in u-boot code for SoCs
having FMAN-v3(v3H or v3L) controller due to below reasons-On SoCs that have FMAN-v3H like B4860, default value of
MDIO_CLK_DIV bits in mdio_stat(mdio_cfg) register generates
mdio clock too high (much higher than 2.5MHz), violating the
IEEE specs.
-On SOCs that have FMAN-v3L like T1040, default value of
MDIO_CLK_DIV bits is zero, so MDIO clock is disabled.So, for proper functioninig of MDIO, MDIO_CLK_DIV bits needs to
be properly initialized.
Also this type of initialization is generally done in
PBI(pre-bootloader) phase using rcw.But for chips like T1040
which support deep-sleep, such type of initialization cannot be
done in PBI phase due to the limitation that during deep-sleep
resume, FMAN (MDIO) registers are not accessible in PBI phase.
So, mdio clock initailization must be done as part of u-boot.This initialization code is implemented in memac_phy.c which
gets compiled only for SoCs having FMANv3, so no extra compilation
flag is required.Signed-off-by: Priyanka Jain
Reviewed-by: York Sun -
Increase TXFIFOTHRES field value in TXFILLTUNING register of usb for T4 Rev 2.0.
This decreases data burst rate with which data packets are posted from the TX
latency FIFO to compensate for latencies in DDR pipeline during DMA.
This avoids Tx buffer underruns and leads to successful usb writesSigned-off-by: Ramneek Mehresh
Signed-off-by: Nikhil Badola
Reviewed-by: York Sun -
Fix following compile warnings
fsl_esdhc_spl.c: In function 'mmc_boot':
fsl_esdhc_spl.c:35:10: warning: unused variable 'byte_num' [-Wunused-variable]
fsl_esdhc_spl.c:35:7: warning: unused variable 'i' [-Wunused-variable]
fsl_esdhc_spl.c:34:8: warning: unused variable 'val' [-Wunused-variable]
fsl_esdhc_spl.c:33:6: warning: unused variable 'blklen' [-Wunused-variable]
fsl_esdhc_spl.c:105:7: warning: 'tmp_buf' may be used uninitialized in this
function [-Wuninitialized]Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
Put a delay of 5 millisecond after reset so that ULPI phy
gets enough time to come out of reset. Erratum A007075 applies
to following SOCs and their variants, if any
P1010 rev 1.0
B4860 rev 1.0, 2.0
P4080 rev 2.0, 3.0Signed-off-by: Nikhil Badola
Reviewed-by: York Sun -
Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register
calculation and programming.Signed-off-by: York Sun
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In the current Datasheet for VSC8514 there is a mistake, saying that
the PHY id is 0x70570. The real value in the identifier registers is
0x70670. Linux PHY driver uses 0x70670 also.Signed-off-by: Codrin Ciubotariu
Cc: York Sun
Reviewed-by: York Sun -
For fsl-lsch3 NOR flash boot, IFC CS0 needs to be binded with address
within 32-bit at fist. After u-boot relocates to DDR, CS0 can be binded
to higher address to support large space.Signed-off-by: York Sun
CC: Prabhakar Kushwaha -
Modify code to adapt to both u-qe and qe.
U_QE is a kind of cutted QE.
the differences between U_QE and QE
1. UCC: U_QE supports 2 UCCs while QE supports up to 8 UCCs.
2. IMMR: have different immr base addr.
3. iopin: U_QE doesn't need to config iopin.Signed-off-by: Zhao Qiang
Reviewed-by: York Sun -
CONFIG_SYS_QE_FMAN_FW_ADDR is used to both Fman and QE for microcode address.
Now using CONFIG_SYS_FMAN_FW_ADDR for Fman microcode address,
and CONFIG_SYS_QE_FW_ADDR for QE microcode address.Signed-off-by: Zhao Qiang
Reviewed-by: York Sun -
Set correct phy_type value for second USB controller.
This is required for supporting SOCs having 2 USB controllers
working simultaneously, one with UTMI phy and other with ULPI phySigned-off-by: Nikhil Badola
Reviewed-by: York Sun
20 Apr, 2014
1 commit
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This is dead hardware and no one is interested in making the
necessary changes for upcoming features like generic board or
driver model.Signed-off-by: Daniel Schwierzeck
Cc: Wolfgang Denk
19 Apr, 2014
1 commit
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Signed-off-by: David Mueller
Acked-by: Joe Hershberger
18 Apr, 2014
6 commits
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The ordering of accesses to the rx & tx descriptors is important, yet
the send & recv functions accessed them via regular structure accesses.
This leaves the compiler with the opportunity to reorder those accesses
or to hoist them outside of loops. Prevent that from happening by using
readl & writel to access the descriptors. As a nice bonus, this removes
the need for the driver to care about endianness.Signed-off-by: Paul Burton
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The RX buffers are invalidated when a packet is received, however they
were not suitably cache-line aligned. Allocate them seperately to the
pcnet_priv structure and align to ARCH_DMA_MINALIGN in order to ensure
suitable alignment for the cache invalidation, preventing anything else
being placed in the same lines & lost.Signed-off-by: Paul Burton
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The prior accesses to the descriptor rings & init block via cached
memory had a few issues:- The memory needs cache flushes or invalidation at the appropriate
times, but was not necessarily aligned on cache line boundaries.
This could lead to data being incorrectly lost or written back to
RAM at the wrong time.- There are points where ordering of writes to the memory is
important, but because it's cached memory the pcnet controller
would see cache lines written back ordered by address. This could
occasionally lead to hardware seeing descriptors in an incorrect
state.- Flushing the cache constantly is inefficient.
So, to avoid all of those issues simply access the descriptors & init
block via uncached memory. The MIPS-specific UNCACHED_SDRAM macro is
used to do this (retrieving an address in kseg1) as I could see no
existing generic solution. Since the MIPS Malta board is the only user
of the pcnet driver, hopefully this doesn't matter.Signed-off-by: Paul Burton
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Enough time has passed since this board was moved to Orphan. Remove.
- Remove board/lubbock/*
- Remove include/configs/lubbock.h
- Cleanup defined(CONFIG_LUBBOCK)
- Move the entry from boards.cfg to doc/README.scrapyardSigned-off-by: Masahiro Yamada
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Enough time has passed since these boards were moved to Orphan. Remove.
- Remove board/RPXlite/*
- Remove board/RPXClassic/*
- Remove include/configs/RPXlite.h
- Remove include/configs/RPXClassic.h
- Clean-up defined(CONFIG_RPXCLASSIC)
- Move the entry from boards.cfg to doc/README.scrapyardSigned-off-by: Masahiro Yamada
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Signed-off-by: Masahiro Yamada
Cc: Scott Wood
14 Apr, 2014
1 commit
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This is regression of commit 2035d77d i2c: sh_i2c: Update to new CONFIG_SYS_I2C framework
Before commit 2035d77d, i2c probe command works properly on kzm9g board.
KZM-A9-GT# i2c probe
Valid chip addresses: 0C 12 1D 32 39 3D 40 60After commit 2035d77d, i2c probe command does not work.
KZM-A9-GT# i2c probe
Valid chip addresses: 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7Fsh_i2c_probe() calls sh_i2c_read(), but read length is 0. So acutally it does not read device at all. This patch prepares dummy buffer and read data into it.
Signed-off-by: Tetsuyuki Kobayashi
Acked-by: Heiko Schocher
Signed-off-by: Nobuhiro Iwamatsu
08 Apr, 2014
1 commit
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Conflicts:
arch/arm/cpu/arm926ejs/mxs/Makefile
include/configs/trats.h
include/configs/trats2.h
include/mmc.h
04 Apr, 2014
1 commit
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Conflicts:
arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg
arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfgSigned-off-by: Stefano Babic
03 Apr, 2014
1 commit
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Commit 2faf5fb82ed6 introduced a regression that causes a data
abort when running scsi init followed by scsi reset.There are 2 problems with the original commit
1) ALLOC_CACHE_ALIGN_BUFFER() allocates memory on the stack but is
assigned to ataid[port] and used by other functions.
2) The function ata_scsiop_inquiry() tries to free memory which was
never allocated on the heap.Fix these problems by using tmpid as a temporary cache aligned buffer.
Allocate memory separately for ataid[port] and re-use it if required.Fixes: 2faf5fb82ed6 (ahci: Fix cache align error messages)
Reported-by: Eli Nidam
Signed-off-by: Roger Quadros
02 Apr, 2014
6 commits
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1. The Data timeout counter value in eSDHC_SYSCTL register is
not working as it should be, so add quirks to enable this
workaround to fix it to the max value 0xE.2. Add CONFIG_SYS_FSL_ERRATUM_ESDHC111 to enable its workaround.
* Update of patch for change mmc interface by
Pantelis AntoniouSigned-off-by: Haijun Zhang
Acked-by: Pantelis Antoniou -
The controller reset is performed now if command error occurs.
This commit adds the reset for the case of data related errors too.Signed-off-by: Andrew Gabbasov
Acked-by: Pantelis Antoniou -
Calculation of the timeout value should be based on actual clock value,
written to controller registers. Since mmc->tran_speed is either the
maximum allowed speed, or the preliminary value, that is be not yet
set to registers, the actual timeout, taken by the controller, based
on its clock settings, may be much longer than expected, based on
mmc->tran_speed value. In particular it happens at early initialization
stage, when typical value of mmc->tran_speed is 20MHz or 26MHz, while
actual clock setting, configured in the controller, is 400kHz.
It's more correct to use mmc->clock value for timeout calculation instead.Signed-off-by: Andrew Gabbasov
Acked-by: Pantelis Antoniou -
Some eMMC chips may need the RST_n_FUNCTION bit set to a non-zero value
in order for warm reset of the system to work. Details on this being
required will be part of the eMMC datasheet. Also add using this
command to the dra7xx README.* Whitespace fix by panto
Signed-off-by: Tom Rini
Acked-by: Pantelis Antoniou -
Signed-off-by: Nobuhiro Iwamatsu
Reported-by: Masahiro Yamada
Acked-by: Pantelis Antoniou -
BY commit "mmc: Split mmc struct, rework mmc initialization (v2)",
sh_mmcif has compile error. This fixes compile error.Signed-off-by: Nobuhiro Iwamatsu
CC: Pantelis Antoniou
Reported-by: Masahiro Yamada
Acked-by: Pantelis Antoniou
01 Apr, 2014
1 commit
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Implement a callback to toggle the slot power supply. The callback
can be overriden in case some more complex power supply for the slot
was implemented in hardware, yet for the usual case, one can define
a GPIO which toggles the power to the slot.Signed-off-by: Marek Vasut
Cc: Stefano Babic
Cc: Fabio Estevam
Cc: Liu Ying
