Eric Lee / smarc-uboot

05 May, 2015

16 commits

  • 3285e6cbc   powerpc/t2080qds: enable eSDHC peripheral clock support ... Browse Code »
    34

    Enable eSDHC peripheral clock support. u-boot and linux will
    use SD clock generated by peripheral clock instead of platform
    clock.

    Signed-off-by: Yangbo Lu
    Cc: York Sun
    Cc: Pantelis Antoniou
    Reviewed-by: York Sun

    Yangbo Lu
     
  • 2d9ca2c72   mmc: fsl_esdhc: Add peripheral clock support ... Browse Code »
    12

    The SD clock could be generated by platform clock or peripheral
    clock for some platforms. This patch adds peripheral clock
    support for T1024/T1040/T2080. To enable it, define
    CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK.

    Signed-off-by: Yangbo Lu
    Cc: York Sun
    Cc: Pantelis Antoniou
    Reviewed-by: York Sun

    Yangbo Lu
     
  • b46cf1b17   powerpc/t2080qds: enable eSDHC adapter card type identification ... Browse Code »

    Enable eSDHC adapter card type identification and this will do
    some corresponding operations and set 'adapter-type' property
    for device tree according SDHC Card ID.

    Signed-off-by: Yangbo Lu
    Cc: York Sun
    Cc: Pantelis Antoniou
    Reviewed-by: York Sun

    Yangbo Lu
     
  • 5a8dbdc6b   mmc: fsl_esdhc: Add adapter card type identification support ... Browse Code »

    Add adapter card type identification support by reading
    FPGA STAT_PRES1 register SDHC Card ID[0:2] bits. To use this function,
    define CONFIG_FSL_ESDHC_ADAPTER_IDENT.

    Signed-off-by: Yangbo Lu
    Cc: York Sun
    Cc: Pantelis Antoniou
    [York Sun: resolve conflicts in README.fsl-esdhc]
    Reviewed-by: York Sun

    Yangbo Lu
     
  • fd3a78a53   board/t2080rdb: reset cs4315 phy ... Browse Code »

    CS4315 PHY doesn't support phy-reset by software, it
    needs to reset it by hardware via CPLD control.

    Signed-off-by: Shengzhou Liu
    Reviewed-by: York Sun

    Shengzhou Liu
     
  • 1a56fcea9   fsl/deepsleep: avoid the DDR restore from being optimized out ... Browse Code »

    Function dp_ddr_restore is to restore the first 128-byte space
    of DDR. However those codes may be optimized out by compiler
    since the destination address is at 0x0. In order to avoid
    compiler optimization, we restore the space from high address,
    which is not at 0x0, to low address.

    Signed-off-by: Tang Yuantian
    Reviewed-by: York Sun

    Tang Yuantian
     
  • 438031e1b   powerpc/mpc85xx: Don't deref NULL if qman portal lacks cell-index ... Browse Code »

    Signed-off-by: Scott Wood
    Cc: Madalin-Cristian Bucur
    Reviewed-by: York Sun

    Scott Wood
     
  • ea753267d   board/t102x: use fdt_setprop_string instead of fdt_setprop ... Browse Code »

    Use fdt_setprop_string instead of fdt_setprop to fix string length.

    Signed-off-by: Shengzhou Liu
    Reviewed-by: York Sun

    Shengzhou Liu
     
  • ac337168a   powerpc: add 2 common dcache assembly functions ... Browse Code »
    55

    This patch defines the 2 flush_dcache_range and invalidate_dcache_range
    functions for all the powerpc architecture. Their implementation is
    borrowed from the kernel's misc_32.S file and replace the ones from
    mpc86xx and ppc4xx since they were equivalent.

    This is a fix for the problem introduced by this patch:
    http://patchwork.ozlabs.org/patch/448849/

    Signed-off-by: Valentin Longchamp
    Reviewed-by: Tom Rini
    Reviewed-by: York Sun

    Valentin Longchamp
     
  • e8a7f1c32   powerpc/t1023rdb: Add T1023 RDB board support ... Browse Code »

    T1023RDB is a Freescale Reference Design Board that hosts the T1023 SoC.

    T1023RDB board Overview
    -----------------------
    - T1023 SoC integrating two 64-bit e5500 cores up to 1.4GHz
    - CoreNet fabric supporting coherent and noncoherent transactions with
    prioritization and bandwidth allocation
    - Memory: 2GB Micron MT40A512M8HX unbuffered 32-bit fixed DDR4 without ECC
    - Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC
    - Ethernet interfaces:
    - one 1G RGMII port on-board(RTL8211F PHY)
    - one 1G SGMII port on-board(RTL8211F PHY)
    - one 2.5G SGMII port on-board(AQR105 PHY)
    - PCIe: Two Mini-PCIe connectors on-board.
    - SerDes: 4 lanes up to 10.3125GHz
    - NOR: 128MB S29GL01GS110TFIV10 Spansion NOR Flash
    - NAND: 512MB S34MS04G200BFI000 Spansion NAND Flash
    - eSPI: 64MB S25FL512SAGMFI010 Spansion SPI flash.
    - USB: one Type-A USB 2.0 port with internal PHY
    - eSDHC: support SD/MMC card and eMMC on-board
    - 256Kbit M24256 I2C EEPROM
    - RTC: Real-time clock DS1339 on I2C bus
    - UART: one serial port on-board with RJ45 connector
    - Debugging: JTAG/COP for T1023 debugging

    As well updated T1024RDB to add T1023RDB.

    Signed-off-by: Shengzhou Liu
    [York Sun: fix defconfig files]
    Reviewed-by: York Sun

    Shengzhou Liu
     
  • 1d0b59a9b   fsl/pci: Set CFG_READY for PCIe v3.0 and later ... Browse Code »

    Freescale PCIe controllers v3.0 and later need to set bit
    CFG_READY to allow all inbound configuration transactions
    to be processed normally when in EP mode. However, bit
    CFG_READY has been moved from PCIe configuration space to
    CCSR PCIe configuration register comparing previous version.
    The patch is to set this bit according to PCIe version.

    Signed-off-by: Ed Swarthout
    Signed-off-by: Roy Zang
    Signed-off-by: Minghuan Lian
    Reviewed-by: York Sun

    Minghuan Lian
     
  • 5066e6284   T2080QDS/PCIe: Soft Reset PCIe on T2080QDS for down-training issue ... Browse Code »

    T2080QDS PEX1/Slot#1 will down-train from x4 to x2,
    with SRDS_PRTCL_S1 = 0x66 and SRDS_PRTCL_S2 = 0x15.
    Soft reset PCIe can fix this issue.

    Signed-off-by: Zhao Qiang
    Reviewed-by: York Sun

    Zhao Qiang
     
  • 373762c34   powerpc/t4rdb: Add SD boot support for T4240RDB board ... Browse Code »

    This patch adds SD boot support for T4240RDB board. SPL
    framework is used. PBL initializes the internal RAM and
    copies SPL to it. Then SPL initializes DDR using SPD and
    copies u-boot from SD card to DDR, finally SPL transfers
    control to u-boot.

    Signed-off-by: Chunhe Lan
    [York Sun: Fix T4240RDB_SDCARD_defcofig]
    Reviewed-by: York Sun

    Chunhe Lan
     
  • 0dc78ff85   drivers: usb: fsl: Workaround for Erratum A004477 ... Browse Code »

    Add a delay of 1 microsecond before issuing soft reset to the
    controller to let ongoing ULPI transaction complete.
    This prevents corruption of ULPI Function Control Register which
    eventually prevents phy clock from entering to low power mode

    Signed-off-by: Nikhil Badola
    Reviewed-by: York Sun

    Nikhil Badola
     
  • 7fc63cca6   mpc85xx/T4240EMU: Remove T4240EMU board ... Browse Code »
    38

    T4240 SoC has been available for a long time. Emulator support
    is no longer needed.

    Signed-off-by: York Sun

    York Sun
     
  • e1bfd1c6b   powerpc/mpc85xx: Use GOT when loading IVORs post-relocation ... Browse Code »

    Commit 96d2bb952bb ("powerpc/mpc85xx: Don't relocate exception vectors")
    simplified IVOR initialization a bit too much, failing to use the
    post-relocation offset. This doesn't cause a problem with normal NOR
    boot, in which both the pre-relocation and post-relocation addresses
    are 64 KiB aligned. However, if TEXT_BASE is only 4 KiB aligned, such
    as for NAND/SD/etc. boot on some targets, as well as the QEMU target,
    the post-relocation address will not be the same in the lower 16 bits,
    as reserve_uboot() ensures that the relocation address is always 64
    KiB aligned even if the pre-relocation address was not.

    Use the GOT to get the proper post-relocation offsets.

    Fixes: 96d2bb952bb ("powerpc/mpc85xx: Don't relocate exception vectors")
    Signed-off-by: Scott Wood
    Cc: Alexander Graf
    Cc: Shaohui Xie
    Tested-by: Shaohui Xie
    Reviewed-by: York Sun

    Scott Wood
     

29 Apr, 2015

24 commits