28 Nov, 2018
2 commits
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In case ocotp error bit is set, clear it.
This is a workaround to ocotp error bit.Signed-off-by: Peng Fan
(cherry picked from commit 781f2d8febe954b2ef3e51b6a2eebcfbf24b08eb) -
compile waring info is as below:
arch/arm/mach-imx/imx8/parser.c: In function ‘mmc_load_image_parse_container’:
arch/arm/mach-imx/imx8/parser.c:244:1: warning: control reaches end of non-void function [-Wreturn-type]
}
^previouse patch change ID:
I40a791d5b5b1eba6a0170d6853626fb546be4b2cChange-Id: Ia605df11beab42e720fff6442a11b1e4b25ac209
Signed-off-by: faqiang.zhu
27 Nov, 2018
1 commit
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The SPL loads the FIT image FDT part to an address related with the device
block length. This length is 512 for SD/MMC and is 1 for other devices
like SDP, NOR, NAND, SPI, etc.
When signing FIT image, we use fixed address caculated by SD/MMC block length
to sign FDT part. Thus, when booting through uuu, this causes mismatch and
gets authentication failed.Fix the issue by providing a override function for this FIT buffer address.
When secure boot is enabled, adjust the addresses of other devices to be same
with SD/MMC.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit 710efd3ccb99e144bd30af8e1ee46459b4a54dd6)
23 Nov, 2018
2 commits
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If OP-TEE is loaded by ATF, u-boot will add
optee device tree node in th edtb so that
Linux can loads OP-TEE driver.Signed-off-by: Silvano di Ninno
(cherry picked from commit 441c23698ffd5c90c6421113da55fae420072473) -
u-boot currently needs information from ATF to know if
OP-TEE os has been loaded.
this information is transmitted via bootargs.
this patch enables saving those bootargs into a structure.Signed-off-by: Silvano di Ninno
(cherry picked from commit 697cfe9dbdc079b68d8b5685b728a7283c837607)
21 Nov, 2018
1 commit
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To enable SPL+CONTAINER format on android auto with tee, after SPL load
container, SPL need to check rpmb keyblob and copy it to secure memory
for latter use.Change-Id: I40a791d5b5b1eba6a0170d6853626fb546be4b2c
Signed-off-by: faqiang.zhu
19 Nov, 2018
1 commit
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Some platforms don't have alias for usb1 device, so when initialize the
second controller, its seq is allocated by u-boot automatically.
This introduces a problem if the initialization of first controller is failed,
for example nothing connect to first controller, then the seq allocated
for second controller is 0 not 1. EHCI driver uses the seq as index for
USB controller and phy, so it will cause initialization problem for second
controller.Fix the issue by adding the usb1 alias for second USB controller.
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit fe21a1ab93d0788017ec58905e3273c9ab0f5a67)
16 Nov, 2018
1 commit
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Enable dm usb using the base board otg usb port for fastboot usage
Signed-off-by: Peng Fan
Reviewed-by: Ye Li
15 Nov, 2018
4 commits
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Enable dm serial for xen uboot.
Log as below:
#xl console 1
MMC: FSL_SDHC: 0
Loading Environment from ... *** Warning - bad CRC, using default environmentFailed (-5)
In: serial@5a060000
Out: serial@5a060000
Err: serial@5a060000
flash target is MMC:0
Fastboot: Normal
Normal Boot
=>Signed-off-by: Peng Fan
Reviewed-by: Peng Fan
Reviewed-by: Flynn xu -
Update mem map table for xen uboot.
xen console and some magic pages needs to be mappe as normal memory.Signed-off-by: Peng Fan
Reviewed-by: Peng Fan
Reviewed-by: Flynn xu -
Introduce new hypercalls
Signed-off-by: Peng Fan
Reviewed-by: Peng Fan
Reviewed-by: Flynn xu -
Introduce xen header files from Linux Kernel commit
e2b623fbe6a3("Merge tag 's390-4.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux")Signed-off-by: Peng Fan
Reviewed-by: Peng Fan
Reviewed-by: Flynn xu
14 Nov, 2018
1 commit
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Current flexspi clock root is set to 25Mhz OSC, but the flash can support
to 166Mhz clock, so change the flexspi clock root to system PLL1 100Mhz
clock to increase speed.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
12 Nov, 2018
2 commits
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Add support for fastboot variable 'at-vboot-state', it's composed
by 6 sub-variable: 'bootloader-locked', 'bootloader-min-versions',
'avb-perm-attr-set', 'avb-locked', 'avb-unlock-disabled' and
'avb-min-versions'.Test: All 'at-vboot-state' variables are returned
correctly on imx7d_pico and AIY.Change-Id: Ibb855cbcc7c41657af62dafb98a96c4dfb96ef22
Signed-off-by: Ji Luo -
Align the callback to ARM64 environment for
Trusty OS.TEST: AIY-3G & AIY-1G board's TIPC and AVB handler
works.Change-Id: I65806f56267a4a9278db04a462e351da181618cc
Signed-off-by: Haoran.Wang
09 Nov, 2018
3 commits
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Before parsing the image header, try to check if there is a container and
validate it first. If no (valid) container then as a fall-through parse
the image as before.Signed-off-by: Abel Vesa
Reviewed-by: Ye Li -
The check for CONFIG_SPL_SPI_LOAD is fixed, get rid of ret local variable
(that's actually a bug) and fix the length for the spi_flash_read call.Signed-off-by: Abel Vesa
Reviewed-by: Ye Li -
According to SCFW API requirement, when setting the clock parent,
the clock must be disabled. Otherwise it will return ERR_BUSY.When using SPL booting on iMX8QXP, both SPL and regular u-boot will
init the USDHC clock. So the second one in regular u-boot will fail
if we don't disable the clock before setting the parent.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
07 Nov, 2018
2 commits
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This intends to replace the FIT image support since that cannot be
authenticated. Instead, we append another container at the end of
flash.bin, this new one containing a new container with two
images representing the ATF and uboot proper.Signed-off-by: Abel Vesa
Reviewed-by: Ye Li -
Since from B0 TO, there is a Mirror of JTAG ID register added in
SIM. We can read the part revision from this register.
Update codes to use this register.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
03 Nov, 2018
9 commits
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Refact the i.MX8MQ dram init flow to reuse the common dram
driver used by i.MX8MM.Signed-off-by: Bai Ping
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Sometimes, SPL need to pass the trained FSP drate to ATF
if DDR PHY bypass mode is not enabled. So add a fsp_table
to pass these info to ATF. additionally, add more clock
frequency point config to support for code reuse for i.MX8MQ.Signed-off-by: Bai Ping
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Change the dram_pll_init function API to make it same
as i.MX8MM, so the dram init flow can use call the same
API for these two different SOC.Signed-off-by: Bai Ping
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When running with OPTEE, the MMU table in u-boot does not remove the OPTEE
memory from its settings. So ARM speculative prefetch in u-boot may access
that OPTEE memory. Due to trust zone is enabled by OPTEE and that memory
is set to secure access, then the speculative prefetch will fail and cause
various memory issue in u-boot.
The fail address register and int_status register in trustzone has logged
that speculative access from u-boot.Signed-off-by: Ye Li
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Generate the key blob and store it to the last block of boot1 partition
after setting the rpmb key. The key blob should be checked in spl and be
passed to Trusty OS if it's valid. If the key blob are damaged, RPMB
storage proxy service will return fail and should make the device hang.Test: Build and boot ok on imx8qm/qxp.
Change-Id: Ia274cd72109ab6ae15920e91b2a2008e1f1e667c
Signed-off-by: Ji Luo -
Add implementation necessary for supporting SPL on QXP
ARM2 board with dynamic offset detection from container header.Signed-off-by: Teo Hall
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If the resource is not owned by current partition, not assign it
to DomU.Signed-off-by: Peng Fan
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Align the new pinfunc names with header file for all iMX7ULP EVK and ARM2
DTS files.
Also update the EVK DTS files to align with kernel for Rev A3
board. Removed the extcon node for USB ID, since A3 board uses USB ID pin
not GPIO.Signed-off-by: Ye Li
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i.MX7ULP B0 silicon has below updates in iomux
- GPIO function input buffer enable (IBE)/output buffer enable (OBE) is
now controlled by RGPIO module. IOMUXC IBE/OBE is used as an override.
- LPUART2_TX (I/O) to PTB12 (ALT4)
- LPUART2_RX (I) to PTB13 (ALT4)
- USB0_ID (I) to PTC13 (ALT11), PTC18 (ALT11) and PTC19 (ALT10)
- VIU_DE (I) to PTC18 (ALT12), PTC19 (ALT12) and PTE5 (ALT12)
- RTC_CLKOUT (O) to PTB5 (ALT11) and PTB14 (ALT11)
- SEC_VIO_B (I) to PTB4 (ALT11)
- Added new Input Selection Registers
PSMI1_USB0_ID Address: 0x40ac_0338 To select USB_ID input pad/source
PSMI1_VIU_DE Address: 0x40ac_033c To select VIU_DE input pad/sourceCopy the imx7ulp-pinfunc.h from latest kernel dts
(commit 18cdeadfe1967ea33d3bdfc7ccead6d6d06a98a6), and update
the mx7ulp-pins.h accordingly.Signed-off-by: Ye Li
29 Oct, 2018
1 commit
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Update API files generated from latest SCFW commit:
commit b5dbcf59157cf758da2b96c395e3f4cb2674437f
Author: Ranjani Vaidyanathan
Date: Sat Oct 27 02:04:47 2018 -0500SCF-248 Fix Linux boot fail on iMX8QX
Signed-off-by: Ye Li
25 Oct, 2018
2 commits
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Add DDR3 init codes, board codes, defconfig and DTS into u-boot.
Basic modules are ready: SD, UART, I2C, USB host and NAND.There is a FPGA on this board. It controls WDOG_B, and ENET PHY RESET.
So reset and ethernet won't work at default.Signed-off-by: Ye Li
Acked-by: Peng Fan -
Added two DRAM PLL frequencies 266Mhz and 167Mhz output support.
Signed-off-by: Ye Li
23 Oct, 2018
3 commits
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When domu-init-ignore-poweroff set to yes, initially not power off
resources owned by DomU.When supporting M4 + Android Auto, M4 and Android Auto shared display,
but currently no partition created in M4 for display, so
scu_rm will power off the display and cause android auto error.
Let ignore power off first.Signed-off-by: Peng Fan
Reviewed-by: Ye Li -
Stop the usb device controller before enter kernel, this is required
to make kernel can properly init usb controller with it's in stopped
state.Suggested-by: Ye.Li
Reviewed-by: Ye Li
Signed-off-by: Li Jun -
It is highly recommended to set the PRIBLOB bitfield to 0x3 once your
encrypted boot image has booted up, this prevents the generation of new
blobs that can be used to decrypt an encrypted boot image. The PRIBLOB is
a sticky type bit and cannot be changed until the next power on reset.Add the set_priblob_bitfield U-Boot command to prevent the generation of
new blobs.Signed-off-by: Clement Le Marquis
Acked-by: Ye Li
18 Oct, 2018
2 commits
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According to iMX8MM datasheet (IMX8MMIEC_Rev_D and IMX8MMCEC_Rev_D),
the speed grading for imx8mm is 800Mhz, 1.2Ghz, 1.6Ghz and 1.8Ghz.
Update them to get_cpu_speed_grade_hz function.Signed-off-by: Ye Li
Reviewed-by: Peng Fan -
Power down the A53 cores for dual core and single core iMX8MM parts
to save power.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
17 Oct, 2018
2 commits
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According the part type, delete A53 cores' nodes and disable VPU
decoder/encoder nodes from kernel DTB.Signed-off-by: Ye Li
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iMX8MM family has several variant parts below.
Add CPU type and relevant updatesi.MX 8M Mini Quad Full featured, 4x A53
i.MX 8M Mini QuadLite No VPU, 4x A53
i.MX 8M Mini Dual Full featured, 2x A53
i.MX 8M Mini DualLite No VPU, 2x A53
i.MX 8M Mini Solo Full featured, 1x A53
i.MX 8M Mini SoloLite No VPU, 1x A53Signed-off-by: Ye Li
16 Oct, 2018
1 commit
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Since commit 8891410c729b ("MLK-19848 mx6dq: Fix chip version issue for
rev1.3") it's not possible to call the HAB API functions on i.MX6DQ
SoC Rev 1.3:Authenticate image from DDR location 0x12000000...
undefined instruction
pc : [] lr : []
reloc pc : [] lr : []
sp : 8ef444a8 ip : 126e8068 fp : 8ff59aa8
r10: 8ffd51e4 r9 : 8ef50eb0 r8 : 006e8000
r7 : 00000000 r6 : 126ea01f r5 : 0000002b r4 : 126e8000
r3 : 412c00dd r2 : 00000001 r1 : 00000001 r0 : 00000063
Flags: nzCv IRQs off FIQs off Mode SVC_32
Resetting CPU ...resetting ...
The hab.h code is defining the HAB API base address according to the
old SoC revision number, thus failing when calling the HAB API
authenticate_image() function.Fix this issue by using mx6dq rev 1.3 instead of mx6dq rev 1.5.
Signed-off-by: Breno Lima
Reviewed-by: Ye Li
