16 Aug, 2017

1 commit


12 Jul, 2017

1 commit

  • Change is consistent with other SOCs and it is in preparation
    for adding SOMs. SOC's related files are moved from cpu/ to
    mach-imx/.

    This change is also coherent with the structure in kernel.

    Signed-off-by: Stefano Babic

    CC: Fabio Estevam
    CC: Akshay Bhat
    CC: Ken Lin
    CC: Marek Vasut
    CC: Heiko Schocher
    CC: "Sébastien Szymanski"
    CC: Christian Gmeiner
    CC: Stefan Roese
    CC: Patrick Bruenn
    CC: Troy Kisky
    CC: Nikita Kiryanov
    CC: Otavio Salvador
    CC: "Eric Bénard"
    CC: Jagan Teki
    CC: Ye Li
    CC: Peng Fan
    CC: Adrian Alonso
    CC: Alison Wang
    CC: Tim Harvey
    CC: Martin Donnelly
    CC: Marcin Niestroj
    CC: Lukasz Majewski
    CC: Adam Ford
    CC: "Albert ARIBAUD (3ADEV)"
    CC: Boris Brezillon
    CC: Soeren Moch
    CC: Richard Hu
    CC: Wig Cheng
    CC: Vanessa Maegima
    CC: Max Krummenacher
    CC: Stefan Agner
    CC: Markus Niebel
    CC: Breno Lima
    CC: Francesco Montefoschi
    CC: Jaehoon Chung
    CC: Scott Wood
    CC: Joe Hershberger
    CC: Anatolij Gustschin
    CC: Simon Glass
    CC: "Andrew F. Davis"
    CC: "Łukasz Majewski"
    CC: Patrice Chotard
    CC: Nobuhiro Iwamatsu
    CC: Hans de Goede
    CC: Masahiro Yamada
    CC: Stephen Warren
    CC: Andre Przywara
    CC: "Álvaro Fernández Rojas"
    CC: York Sun
    CC: Xiaoliang Yang
    CC: Chen-Yu Tsai
    CC: George McCollister
    CC: Sven Ebenfeld
    CC: Filip Brozovic
    CC: Petr Kulhavy
    CC: Eric Nelson
    CC: Bai Ping
    CC: Anson Huang
    CC: Sanchayan Maity
    CC: Lokesh Vutla
    CC: Patrick Delaunay
    CC: Gary Bisson
    CC: Alexander Graf
    CC: u-boot@lists.denx.de
    Reviewed-by: Fabio Estevam
    Reviewed-by: Christian Gmeiner

    Stefano Babic
     

14 Apr, 2017

1 commit


20 Mar, 2017

1 commit


16 Dec, 2016

4 commits

  • Currently a divider of 6 has been used, leading to following NAND
    Flash Controller (NFC) clocks:
    VF61: 27.7 MHz (166.7MHz bus clock)
    VF50: 22 MHz (132MHz bus clock)

    The NAND Flash Memory used on VF50 allows to use clock speed of
    up to 33MHz, while the Flash Memory of VF61 allows 50MHz. We can
    use the same divider of 4 on both modules to configure the maximal
    possible clock speeds:
    VF61: 41.7 MHz
    VF50: 33 MHz

    Signed-off-by: Stefan Agner

    Stefan Agner
     
  • Use the same preprocessor define to enable clocks as we use to
    enable the driver. Make sure that the necessary PLL's are on
    (they get enabled by boot ROM by default, so this is more for
    completness).

    Signed-off-by: Stefan Agner

    Stefan Agner
     
  • Use device-tree fixup to communicate the MTD partitions to the
    kernel. U-Boot's mtdparts environment variable will be used as
    partition source for the device-tree based partition table too.

    Signed-off-by: Stefan Agner

    Stefan Agner
     
  • The config block support currently uses the ft_board_setup function
    to patch the device tree with config block information. However, this
    does not allow to patch the device tree with board specific information.
    Rename the common setup function to ft_common_board_setup and use the
    call it from the board files directly.

    Signed-off-by: Stefan Agner

    Stefan Agner
     

29 Nov, 2016

2 commits


26 Oct, 2016

1 commit


25 Nov, 2015

1 commit


15 Oct, 2015

1 commit

  • Commit 3f353cecc ("vf610: refactor DDRMC code") changed the original
    bstlen field from 3 to 0.

    Restore the original value for proper behaviour.

    Based on the patch from Anthony Felice
    for the vf610twr board.

    Reported-by: Stefan Agner
    Signed-off-by: Fabio Estevam

    Fabio Estevam
     

02 Oct, 2015

1 commit


08 Jun, 2015

4 commits


24 Apr, 2015

2 commits

  • Enable USB support on Toradex Colibri Vybrid Modules.

    Signed-off-by: Sanchayan Maity
    Acked-by: Marek Vasut

    Sanchayan Maity
     
  • This adds initial support for Colibri VF50/VF61 based on Freescale
    Vybrid SoC.

    - CPU clocked at 396/500 MHz
    - DDR3 at 396MHz
    - for VF50, use PLL2 as memory clock (synchronous mode)
    - for VF61, use PLL1 as memory clock (asynchronous mode)
    - Console on UART0 (Colibri UART_A)
    - Ethernet on FEC1
    - PLL5 based RMII clocking (E.g. No external crystal)
    - UART_A and UART_C I/O muxing
    - Boot from NAND by default

    Tested on Colibri VF50/VF61 booting using serial loader over UART.

    Signed-off-by: Sanchayan Maity
    Acked-by: Stefan Agner

    Sanchayan Maity