13 May, 2015

1 commit

  • By making the board selections optional, every defconfig will include
    the board selection when running savedefconfig so if a new board is
    added to the top of the list of choices the former top's defconfig will
    still be correct.

    Signed-off-by: Joe Hershberger
    Cc: Masahiro Yamada
    Acked-by: Stephen Warren
    Cc: Tom Rini

    Joe Hershberger
     

30 Apr, 2015

2 commits


19 Apr, 2015

2 commits


17 Apr, 2015

1 commit

  • Support running U-Boot as a coreboot payload. Tested peripherals include:

    - Video (HDMI and DisplayPort)
    - SATA disk
    - Gigabit Ethernet
    - SPI flash

    USB3 does not work. This may be a problem with the USB3 PCI driver or
    something in the USB3 stack and has not been investigated So far this is
    disabled. The SD card slot also does not work.

    For video, coreboot will need to run the OPROM to set this up.

    With this board, bare support (running without coreboot) is not available
    as yet.

    Signed-off-by: Simon Glass

    Simon Glass
     

06 Feb, 2015

1 commit


13 Jan, 2015

2 commits


19 Dec, 2014

1 commit

  • Intel Tunnel Creek GPIO register block is compatible with current
    ich6-gpio driver, except the offset and content of GPIO block base
    address register in the LPC PCI configuration space are different.

    Use u16 instead of u32 to store the 16-bit I/O address of the GPIO
    registers so that it could support both Ivybridge and Tunnel Creek.

    Signed-off-by: Bin Meng
    Acked-by: Simon Glass

    Bin Meng
     

14 Dec, 2014

2 commits


25 Nov, 2014

2 commits


21 Nov, 2014

4 commits

  • Enable GPIO support and provide the required GPIO setup information to
    the driver.

    Signed-off-by: Simon Glass

    Simon Glass
     
  • Add support for CAR so that we have memory to use prior to DRAM init.
    On link there is a total of 128KB of CAR available, although some is
    used for the memory reference code.

    Signed-off-by: Simon Glass

    Simon Glass
     
  • On x86 it is common to use 'post codes' which are 8-bit hex values emitted
    from the code and visible to the user. Traditionally two 7-segment displays
    were made available on the motherboard to show the last post code that was
    emitted. This allows diagnosis of a boot problem since it is possible to
    see where the code got to before it died.

    On modern hardware these codes are not normally visible. On Chromebooks
    they are displayed by the Embedded Controller (EC), so it is useful to emit
    them. We must enable this feature for the EC to see the codes, so add an
    option for this.

    Signed-off-by: Simon Glass
    Reviewed-by: Bin Meng

    Simon Glass
     
  • This board is a 'bare' version of the existing 'link 'board. It does not
    require coreboot to run, but is intended to start directly from the reset
    vector.

    This initial commit has place holders for a wide range of features. These
    will be added in follow-on patches and series. So far it cannot be booted
    as there is no ROM image produced, but it does build without errors.

    Signed-off-by: Simon Glass

    Simon Glass