Eric Lee / smarc-uboot

08 Jan, 2020

1 commit

24 Oct, 2019

1 commit

  • 7feafb0ae   ufs: Add Initial Support for UFS subsystem ... Browse Code »

    Add Support for UFS Host Controller Interface (UFSHCI) for communicating
    with Universal Flash Storage (UFS) devices. The steps to initialize the
    host controller interface are the following:

    - Initiate the Host Controller Initialization process by writing to the
    Host controller enable register.
    - Configure the Host Controller base address registers by allocating a
    host memory space and related data structures.
    - Unipro link startup procedure
    - Check for connected device
    - Configure UFS host controller to process requests

    Also register this host controller as a SCSI host controller.

    Taken from Linux Kernel v5.2 (drivers/scsi/ufs/ufshcd.c) and ported to
    U-boot.

    Signed-off-by: Faiz Abbas

    Faiz Abbas
     

12 Aug, 2019

1 commit

11 Jul, 2019

1 commit

  • 914026d25   drivers: pci_ep: Introduce UCLASS_PCI_EP uclass ... Browse Code »
    12

    Introduce new UCLASS_PCI_EP class for handling PCI endpoint
    devices, allowing to set various attributes of the PCI endpoint
    device, such as:
    * configuration space header
    * BAR definitions
    * outband memory mapping
    * start/stop PCI link

    Signed-off-by: Ramon Fried
    Reviewed-by: Simon Glass

    Ramon Fried
     

05 May, 2019

1 commit

12 Apr, 2019

1 commit

  • 432f66fe7   soc: ti: k3: add navss ringacc driver ... Browse Code »

    The Ring Accelerator (RINGACC or RA) provides hardware acceleration to
    enable straightforward passing of work between a producer and a consumer.
    There is one RINGACC module per NAVSS on TI AM65x SoCs.

    The RINGACC converts constant-address read and write accesses to equivalent
    read or write accesses to a circular data structure in memory. The RINGACC
    eliminates the need for each DMA controller which needs to access ring
    elements from having to know the current state of the ring (base address,
    current offset). The DMA controller performs a read or write access to a
    specific address range (which maps to the source interface on the RINGACC)
    and the RINGACC replaces the address for the transaction with a new address
    which corresponds to the head or tail element of the ring (head for reads,
    tail for writes). Since the RINGACC maintains the state, multiple DMA
    controllers or channels are allowed to coherently share the same rings as
    applicable. The RINGACC is able to place data which is destined towards
    software into cached memory directly.

    Supported ring modes:
    - Ring Mode
    - Messaging Mode
    - Credentials Mode
    - Queue Manager Mode

    TI-SCI integration:

    Texas Instrument's System Control Interface (TI-SCI) Message Protocol now
    has control over Ringacc module resources management (RM) and Rings
    configuration.

    The Ringacc driver manages Rings allocation by itself now and requests
    TI-SCI firmware to allocate and configure specific Rings only. It's done
    this way because, Linux driver implements two stage Rings allocation and
    configuration (allocate ring and configure ring) while TI-SCI Message
    Protocol supports only one combined operation (allocate+configure).

    Signed-off-by: Grygorii Strashko
    Signed-off-by: Vignesh R

    Grygorii Strashko
     

20 Feb, 2019

1 commit

07 Dec, 2018

1 commit

15 Nov, 2018

1 commit

  • 8fb49b4c7   dm: Add a new uclass driver for VirtIO transport devices ... Browse Code »
    1

    This adds a new virtio uclass driver for “virtio” [1] family of
    devices that are are found in virtual environments like QEMU,
    yet by design they look like physical devices to the guest.

    The uclass driver provides child_pre_probe() and child_post_probe()
    methods to do some common operations for virtio device drivers like
    device and driver supported feature negotiation, etc.

    [1] http://docs.oasis-open.org/virtio/virtio/v1.0/virtio-v1.0.pdf

    Signed-off-by: Tuomas Tynkkynen
    Signed-off-by: Bin Meng
    Reviewed-by: Simon Glass

    Bin Meng
     

07 Oct, 2018

1 commit

  • 9ff4a3117   Add UCLASS_TEE for Trusted Execution Environment ... Browse Code »

    Adds a uclass to interface with a TEE (Trusted Execution Environment).

    A TEE driver is a driver that interfaces with a trusted OS running in
    some secure environment, for example, TrustZone on ARM cpus, or a
    separate secure co-processor etc.

    The TEE subsystem can serve a TEE driver for a Global Platform compliant
    TEE, but it's not limited to only Global Platform TEEs.

    The over all design is based on the TEE subsystem in the Linux kernel,
    tailored for U-Boot.

    Reviewed-by: Simon Glass
    Tested-by: Igor Opaniuk
    Signed-off-by: Jens Wiklander

    Jens Wiklander
     

01 Oct, 2018

1 commit

30 Sep, 2018

1 commit

  • 5381c2856   drivers: Add board uclass ... Browse Code »

    Since there is no canonical "board device" that can be used in board
    files, it is difficult to use DM function for board initialization in
    these cases.

    Hence, add a uclass that implements a simple "board device", which can
    hold devices not suitable anywhere else in the device tree, and is also
    able to read encoded information, e.g. hard-wired GPIOs on a GPIO
    expander, read-only memory ICs, etc. that carry information about the
    hardware.

    The devices of this uclass expose methods to read generic data types
    (integers, strings, booleans) to encode the information provided by the
    hardware.

    Reviewed-by: Simon Glass
    Signed-off-by: Mario Six

    Mario Six
     

29 Sep, 2018

3 commits

28 Sep, 2018

1 commit

11 Aug, 2018

1 commit

  • a63e54ab5   drivers: Add AXI uclass ... Browse Code »

    Add a uclass for AXI (Advanced eXtensible Interface) busses, and a
    driver for the gdsys IHS AXI bus on IHS FPGAs.

    Signed-off-by: Mario Six
    Reviewed-by: Simon Glass

    Mario Six
     

20 Jul, 2018

1 commit

  • 654dd4a84   soc: qualcomm: Add Shared Memory Manager driver ... Browse Code »

    The Shared Memory Manager driver implements an interface for allocating
    and accessing items in the memory area shared among all of the
    processors in a Qualcomm platform.

    Adapted from the Linux driver (4.17)

    Changes from the original Linux driver:
    * Removed HW spinlock mechanism, which is irrelevant
    in U-boot particualar use case, which is just reading from the smem.
    * Adapted from Linux driver model to U-Boot's.

    Cc: Bjorn Andersson
    Signed-off-by: Ramon Fried
    Reviewed-by: Simon Glass

    Ramon Fried
     

04 Jun, 2018

1 commit

30 May, 2018

1 commit

  • 312a10f16   fastboot: Move fastboot to drivers/fastboot ... Browse Code »

    Separate CMD_FASTBOOT from FASTBOOT and move code and configuration to
    drivers/fastboot.

    Switch dependencies on FASTBOOT to USB_FUNCTION_FASTBOOT as anyone who wants
    FASTBOOT before this series wants USB_FUNCTION_FASTBOOT. Split
    USB_FUNCTION_FASTBOOT from FASTBOOT so they retain their existing
    behaviour.

    Signed-off-by: Alex Kiernan
    Reviewed-by: Simon Glass
    Acked-by: Joe Hershberger

    Alex Kiernan
     

28 May, 2018

1 commit

  • 676859432   phy: Add Allwinner A64 USB PHY driver ... Browse Code »

    USB PHY implementation for Allwinner SOC's can be handling
    in to single driver with different phy configs.

    This driver handle all Allwinner USB PHY's start from 4I to
    50I(except 9I). Currently added A64 compatibility more will
    add in next coming patches.

    Current implementation is unable to get pinctrl, clock and reset
    details from DT since the dm code on these will add it future.

    Driver named as phy-sun4i-usb.c since the same PHY logic
    work for all Allwinner SOC's start from 4I to A64 except 9I
    with different phy configurations.

    Signed-off-by: Jagan Teki
    Acked-by: Jun Nie

    Jagan Teki
     

20 Nov, 2017

1 commit

14 Aug, 2017

1 commit

  • 982388eaa   nvme: Add NVM Express driver support ... Browse Code »

    NVM Express (NVMe) is a register level interface that allows host
    software to communicate with a non-volatile memory subsystem. This
    interface is optimized for enterprise and client solid state drives,
    typically attached to the PCI express interface.

    This adds a U-Boot driver support of devices that follow the NVMe
    standard [1] and supports basic read/write operations.

    Tested with a 400GB Intel SSD 750 series NVMe card with controller
    id 8086:0953.

    [1] http://www.nvmexpress.org/resources/specifications/

    Signed-off-by: Zhikang Zhang
    Signed-off-by: Wenbin Song
    Signed-off-by: Bin Meng
    Reviewed-by: Tom Rini

    Zhikang Zhang
     

12 Jul, 2017

2 commits

22 May, 2017

1 commit

10 May, 2017

1 commit

  • 72e5016f8   drivers: phy: add generic PHY framework ... Browse Code »

    The PHY framework provides a set of APIs to control a PHY. This API is
    derived from the linux version of the generic PHY framework.
    Currently the API supports init(), deinit(), power_on, power_off() and
    reset(). The framework provides a way to get a reference to a phy from the
    device-tree.

    Signed-off-by: Jean-Jacques Hiblot
    Reviewed-by: Simon Glass

    Jean-Jacques Hiblot
     

18 Apr, 2017

1 commit

  • 573a3811e   sysreset: psci: support system reset in a generic way with PSCI ... Browse Code »
    1

    If the system is running PSCI firmware, the System Reset function
    (func ID: 0x80000009) is supposed to be handled by PSCI, that is,
    the SoC/board specific reset implementation should be moved to PSCI.
    U-Boot should call the PSCI service according to the arm-smccc
    manner.

    The arm-smccc is supported on ARMv7 or later. Especially, ARMv8
    generation SoCs are likely to run ARM Trusted Firmware BL31. In
    this case, U-Boot is a non-secure world boot loader, so it should
    not be able to reset the system directly.

    Signed-off-by: Masahiro Yamada

    Masahiro Yamada
     

14 Apr, 2017

1 commit

05 Jan, 2017

1 commit

27 Sep, 2016

1 commit

  • 3335786a9   drivers/phy: Add Marvell SerDes / PHY drivers used on Armada 3k ... Browse Code »

    This version is based on the Marvell U-Boot version with this patch
    applied as latest patch:

    Git ID 7f408573: "fix: comphy: cp110: add comphy initialization for usb
    device mode" from 2016-07-05.

    Signed-off-by: Stefan Roese
    Cc: Nadav Haklai
    Cc: Kostya Porotchkin
    Cc: Wilson Ding
    Cc: Victor Gu
    Cc: Hua Jing
    Cc: Terry Zhou
    Cc: Hanna Hawa
    Cc: Haim Boot

    Stefan Roese
     

22 Sep, 2016

1 commit

12 Aug, 2016

1 commit

20 Jun, 2016

1 commit

  • 89c1e2da7   Add a reset driver framework/uclass ... Browse Code »

    A reset controller is a hardware module that controls reset signals that
    affect other hardware modules or chips.

    This patch defines a standard API that connects reset clients (i.e. the
    drivers for devices affected by reset signals) to drivers for reset
    controllers/providers. Initially, DT is the only supported method for
    connecting the two.

    The DT binding specification (reset.txt) was taken from Linux kernel
    v4.5's Documentation/devicetree/bindings/reset/reset.txt.

    Signed-off-by: Stephen Warren
    Acked-by: Simon Glass

    Stephen Warren
     

27 May, 2016

1 commit

  • 6238935d0   Add a mailbox driver framework/uclass ... Browse Code »

    A mailbox is a hardware mechanism for transferring small message and/or
    notifications between the CPU on which U-Boot runs and some other device
    such as an auxilliary CPU running firmware or a hardware module.

    This patch defines a standard API that connects mailbox clients to mailbox
    providers (drivers). Initially, DT is the only supported method for
    connecting the two.

    The DT binding specification (mailbox.txt) was taken from Linux kernel
    v4.5's Documentation/devicetree/bindings/mailbox/mailbox.txt.

    Signed-off-by: Stephen Warren
    Acked-by: Simon Glass

    Stephen Warren
     

19 Apr, 2016

1 commit

  • 8f6952321   memory: Move TI_AEMIF config to KCONFIG ... Browse Code »

    Not all Keystone2 devices has AEMIF NAND controller. So adding Kconfig
    entry for CONFIG_TI_AEMIF and enabling it in respective defconfigs on
    platforms with AEMIF controller.

    Reported-by: Nishanth Menon
    Signed-off-by: Lokesh Vutla
    Reviewed-by: Tom Rini

    Lokesh Vutla
     

02 Apr, 2016

1 commit

  • 04868b407   drivers: Add SPMI bus uclass ... Browse Code »

    Qualcom processors use proprietary bus to talk with PMIC devices -
    SPMI (System Power Management Interface).
    On wiring level it is similar to I2C, but on protocol level, it's
    multi-master and has simple autodetection capabilities.
    This commit adds simple uclass that provides bus read/write interface.

    Signed-off-by: Mateusz Kulikowski
    Reviewed-by: Simon Glass
    Tested-by: Simon Glass

    Mateusz Kulikowski
     

22 Jan, 2016

1 commit

02 Nov, 2015

1 commit

  • 5decbf530   dm: adc: add simple ADC uclass implementation ... Browse Code »

    This commit adds:
    - new uclass id: UCLASS_ADC
    - new uclass driver: drivers/adc/adc-uclass.c

    The new uclass's API allows for ADC operation on:
    * single-channel with channel selection by a number
    * multti-channel with channel selection by bit mask

    ADC uclass's functions:
    * single-channel:
    - adc_start_channel() - start channel conversion
    - adc_channel_data() - get conversion data
    - adc_channel_single_shot() - start/get conversion data
    * multi-channel:
    - adc_start_channels() - start selected channels conversion
    - adc_channels_data() - get conversion data
    - adc_channels_single_shot() - start/get conversion data for channels
    selected by bit mask
    * general:
    - adc_stop() - stop the conversion
    - adc_vdd_value() - positive reference Voltage value with polarity [uV]
    - adc_vss_value() - negative reference Voltage value with polarity [uV]
    - adc_data_mask() - conversion data bit mask

    The device tree can provide below constraints/properties:
    - vdd-polarity-negative: if true: Vdd = vdd-microvolts * (-1)
    - vss-polarity-negative: if true: Vss = vss-microvolts * (-1)
    - vdd-supply: phandle to Vdd regulator's node
    - vss-supply: phandle to Vss regulator's node
    And optional, checked only if the above corresponding, doesn't exist:
    - vdd-microvolts: positive reference Voltage [uV]
    - vss-microvolts: negative reference Voltage [uV]

    Signed-off-by: Przemyslaw Marczak
    Cc: Simon Glass
    Signed-off-by: Minkyu Kang

    Przemyslaw Marczak
     

23 Oct, 2015

1 commit