20 Nov, 2020
1 commit
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* origin/dn_uboot: (14 commits)
Revert "mmc: move mmc_power_cycle() after controller initialization"
Revert "mmc: rework mmc_set_initial_state"
board: freescale: vid.c: add parantheses to fix build warning
net: pfe_eth: read PFE ESBC header flash with spi_flash_read API
lx2160a: Fix address for secure boot headers
...
19 Nov, 2020
2 commits
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This reverts commit db5e48bab9ef90b05da8c4ad396a9a959506b2fe.
The changes needs rework to work on i.mx devices
LFU-40Signed-off-by: Priyanka Jain
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This reverts commit ef959d695523c391a68093550a3bfb8714ab7ac9.
The changes needs rework to work on i.mx devices
LFU-40Signed-off-by: Priyanka Jain
16 Nov, 2020
1 commit
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On imx6Q/imx6DL, we find if config the DTOCV to 0~3, it will impact
cmd6 behavior, after cmd6 get transfer complete interrupt, the data0
line will keep low over 5 seconds. This should be a IC bug on imx6Q/DL.
For other platforms, do not has this issue.To fix this issue, fix the DTOCV to 0xE, the max setting, this also align
with Linux configuration.Signed-off-by: Haibo Chen
Reviewed-by: Ye Li
(cherry picked from commit 6df53e27277d43353cfffd895b7b1c1e1b847ab3)
19 Oct, 2020
1 commit
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Currently, after config the clock rate, delay 10ms, this is quite a rough
method. Check the clock stable status in the present status register is
enough.Tested-by: Ji Luo
Reviewed-by: Peng Fan
Signed-off-by: Haibo Chen
(cherry picked from commit 4e45d2e2f31e559ebdc3ca1d933edfeb60cd7a78)
28 Aug, 2020
2 commits
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Prepare for 3rd merge window of lf_uboot
Signed-off-by: Ye Li
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Prepare for 3rd merge window of lf_uboot
Signed-off-by: Ye Li
27 Aug, 2020
18 commits
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Erratum A-011334: Limited clock dividers for HS400 mode
Description: Due to this erratum, the division ratio options
are limited for HS400 mode. The divider value
(value of SYSCTL[DVS] * value of SYSCTL[SDCLKFS] ) can only be
4, 8, or 12.Workaround: Select the divider value to be 4, 8, or 12.
Signed-off-by: Yangbo Lu
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Each of below functions called by mmc_set_initial_state() will
configure voltage, clock, bus width, and mode through mmc_set_ios(),
before initialize these parameters properly. The right method
should be initialize these parameters properly and set them by
mmc_set_ios() once.- mmc_set_signal_voltage
- mmc_set_clock
- mmc_set_bus_widthSigned-off-by: Yangbo Lu
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The mmc_power_cycle() should be put after controller initialization
because the mmc_power_off() would call mmc_set_clock() which will
configure the controller through mmc_set_ios().Signed-off-by: Yangbo Lu
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The initial clock setting should be through sysctl register only,
while the mmc_set_clock() will call mmc_set_ios() introduce other
configurations like bus width, mode, and so on.Signed-off-by: Yangbo Lu
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If the controller is in HS400 mode, it should exit HS400 mode
properly before switching to any other mode.Signed-off-by: Yangbo Lu
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There was a fix-up for eMMC HS400 stability issue in Linux.
Patch link:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
commit/?id=58d0bf843b49fa99588ac9f85178bd8dfd651b53Description:
Currently only LX2160A eSDHC supports eMMC HS400. According to
a large number of tests, eMMC HS400 failed to work at 150MHz,
and for a few boards failed to work at 175MHz. But eMMC HS400
worked fine on 200MHz. We hadn't found the root cause but
setting eSDHC_DLLCFG0[DLL_FREQ_SEL] = 0 using slow delay chain
seemed to resovle this issue. Let's use this as fixup for now.Introduce the fix-up in u-boot since the issue could be reproduced
in u-boot too.Signed-off-by: Yangbo Lu
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Fix mmc->clock with actual clock which is divided by the
controller, and record it with priv->clock which was removed
accidentally.Signed-off-by: Yangbo Lu
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The process for eMMC HS400 mode for eSDHC is,
1. Perform the Tuning Process at the HS400 target operating frequency.
Latched the clock division value.
2. if read transaction, then set the SDTIMNGCTL[FLW_CTL_BG].
3. Switch to High Speed mode and then set the card clock frequency to
a value not greater than 52Mhz
4. Clear TBCTL[TB_EN],tuning block enable bit.
5. Change to 8 bit DDR Mode
6. Switch the card to HS400 mode.
7. Set TBCTL[TB_EN], tuning block enable bit.
8. Clear SYSCTL[SDCLKEN]
9. Wait for PRSSTAT[SDSTB] to be set
10. Change the clock division to latched value.Set TBCTL[HS 400 mode]
and Set SDCLKCTL[CMD_CLK_CTRL]
11. Set SYSCTL[SDCLKEN]
12. Wait for PRSSTAT[SDSTB] to be set
13. Set DLLCFG0[DLL_ENABLE] and DLLCFG0[DLL_FREQ_SEL].
14. Wait for delay chain to lock.
15. Set TBCTL[HS400_WNDW_ADJUST]
16. Again clear SYSCTL[SDCLKEN]
17. Wait for PRSSTAT[SDSTB] to be set
18. Set ESDHCCTL[FAF]
19. Wait for ESDHCCTL[FAF] to be cleared
20. Set SYSCTL[SDCLKEN]
21. Wait for PRSSTAT[SDSTB] to be set.Signed-off-by: Yangbo Lu
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Add a mmc_hs400_prepare_ddr() interface for controllers
which needs preparation before switching to DDR mode for
HS400 mode.Signed-off-by: Yangbo Lu
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Add a hs400_tuning flag to identify the tuning for HS400 mode.
Signed-off-by: Yangbo Lu
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Clean TBCTL[TB_EN] manually during init since it is not able to
be reset by reset all operation.Signed-off-by: Yangbo Lu
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Support tuning process for eMMC HS200 for eSDHC.
Signed-off-by: Yangbo Lu
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Add a reinit() callback for mmc rescan.
Signed-off-by: Yangbo Lu
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For DM_MMC, the controller re-initialization is needed to
clear old configuration for mmc rescan.Signed-off-by: Yangbo Lu
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The eSDHC adapter card identification and multiplexing configuration
through FPGA had been implemented in both common mmc driver and
fsl_esdhc driver. However it is proper to move these code to board
files and do it during board initialization. The FPGA registers are
also board specific.This patch is to move eSDHC adapter card identification and
multiplexing configuration from mmc driver to specific board files.
And the option CONFIG_FSL_ESDHC_ADAPTER_IDENT is no longer needed.Signed-off-by: Yangbo Lu
[Rebased, Removed T1040QDS change as board does not exist]
Signed-off-by: Priyanka Jain -
The sdhc_adapter of global data has not been used, and we
do not have to use it as global data even we may need it
in the future.Signed-off-by: Yangbo Lu
Reviewed-by: Peng Fan
Reviewed-by: Priyanka Jain -
When eSDHC operates at 3.3v, damage can accumulate in an internal
level shifter at a higher than expected rate. The faster the interface
runs, the more damage accumulates. This issue now is found on LX2160A
eSDHC1 for only SD card.The hardware workaround is recommended to use an on-board level shifter
that is 1.8v on SoC side and 3.3v on SD card side.For boards without hardware workaround, this option could be enabled,
ensuring 1.8v IO voltage and disabling eSDHC if no card.
This option assumes no hotplug, and u-boot has to make all the way to
to linux to use 1.8v UHS-I speed mode if has card.
If you do not want the workaround for better user experience, of course
you can choose to not select it running eSDHC in unsafe mode.Signed-off-by: Yangbo Lu
Acked-by: Peng Fan -
No need to poll register for card inserted status.
Signed-off-by: Yangbo Lu
Acked-by: Peng Fan
26 Aug, 2020
1 commit
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Fix Coverity Issue 5498427. In fsl_esdhc_initialize, leak of memory to
system resource variable 'plat'. Move the fuse check to the beginning
of the function before the resources allocation.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit cfb4e1919db16c5e0de05638032f09674d756350)
25 Aug, 2020
1 commit
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Introduce support for S32V234PCIE board.
Signed-off-by: Stoica Cosmin-Stefan
Signed-off-by: Vicovan Ionut-Valentin
Signed-off-by: Eddy Petrișor
Signed-off-by: Heinz Wrobel
Signed-off-by: Nica Dan
Signed-off-by: Cosmin Oprea
Signed-off-by: Larisa Grigore
Signed-off-by: Tomas Babinec
21 Jul, 2020
1 commit
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The sys_proto.h was added for the fuse checking on iMX6 platform.
To avoid build break on S32, wrap it with CONFIG_MX6.Signed-off-by: Ye Li
16 Jul, 2020
2 commits
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According to eMMC specification v5.1 section 6.4.3, we should issue
CMD1 repeatedly in the idle state until the eMMC is ready even if
mmc_send_op_cond() send CMD1 with argument = 0. Otherwise some eMMC
devices seems to enter the inactive mode after mmc_complete_op_cond()
issued CMD0 when the eMMC device is busy.Signed-off-by: Haibo Chen
Reviewed-by: Peng Fan
(cherry picked from commit fe95905ffed57d617cad81a71ac419d53aaa1ebf)
(cherry picked from commit 2fba3f1cf2972fa403ee359924d8620b1b08f0ef) -
In current code, we add 1ms dealy after each tuning command for standard
tuning method. Adding this 1ms dealy is because USDHC default check the
CMD CRC and DATA line. If detect the CMD CRC, USDHC standard tuning
IC logic do not wait for the tuning data sending out by the card, trigger
the buffer read ready interrupt immediately, and step to next cycle. So
when next time the new tuning command send out by USDHC, card may still
not send out the tuning data of the upper command，then some eMMC cards
may stuck, can't response to any command, block the whole tuning procedure.If do not check the CMD CRC for tuning, then do not has this issue. USDHC
will wait for the tuning data of each tuning command and check them. If the
tuning data pass the check, it also means the CMD line also okay for tuning.So this patch disable the CMD CRC check for tuning, save some time for the
whole tuning procedure.Signed-off-by: Haibo Chen
(cherry picked from commit ba61676ff9f8225ebc0ea33ad9f48862e718fd01)
(cherry picked from commit b76091fde0aa88ba763cfa1db80b72702653c3b2)
16 Jun, 2020
1 commit
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Only enable PER clk is not enough, we also need to enable AHB/IPG clk.
Reviewed-by: Ye Li
Signed-off-by: Peng Fan
06 May, 2020
4 commits
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Secure Storage service in Trusty OS will compute
the encrypted mmc frame and the rpmb proxy inject the frame
to driver directly. So that need to export RPMB related
interface for Secure Storage proxy use.Change-Id: I7f69831a20a440f597d323b610fa615fd4344d05
Signed-off-by: Haoran.Wang
(cherry picked from commit 4d2c1873ce8221e35874265e41dc42a6df169659)
(cherry picked from commit ce4e9dc35ff89a2429224ae6d0ffb4109cb42e28)
(cherry picked from commit 412ece12209e2f916616053ad65b421e95c07955) -
Add the fuse checking in drivers, when the module is disabled in fuse,
the driver will not work.Changed drivers: BEE, GPMI, APBH-DMA, ESDHC, FEC, QSPI, ECSPI, I2C,
USB-EHCI, GIS, LCDIF and EPDC.Signed-off-by: Ye Li
(cherry picked from commit 1704e116f9b39aeb99201919a18bc2b1e19a980e)
(cherry picked from commit 2d3b5df8530cd5ef883750378838dea7c40259af)
(cherry picked from commit 6e8c9ae136bee8ec0121c1db4b935510caad09db)
(cherry picked from commit 99b54a6965904a879afdb6883a519de726cb4e96) -
Should use CONFIG_IS_ENABLED not IS_ENABLED for CLK driver, so it will
check the CONFIG_SPL_CLK when building SPLMove init_clk_usdhc to non-clk driver case, since assigned-clocks properties
will initialize the clocks by clk driver.Signed-off-by: Ye Li
(cherry picked from commit be51cba531a985f6bde70213856ee957b80562dd) -
When sd/mmc work at DDR mode, like HS400/HS400ES/DDR52/DDR50 mode,
the actual clock rate is just half of the expected clock.This patch set the DDR_EN bit first for DDR mode, hardware divide
the usdhc clock automatically, then follow the original sdr clock
setting method.Signed-off-by: Haibo Chen
Signed-off-by: Ye Li
(cherry picked from commit 2a8a0cf0f5d2fcb06d217e3d026219532fed5eb7)
(cherry picked from commit c340cddc28f7a314ae52add5d934c7194a83404c)
03 Apr, 2020
2 commits
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According to the HW team, for some reason the normal clock select code
picks what appears to be a perfectly valid 375KHz SD card clock, based
on the CAR clock source and SDMMC1 controller register settings (CAR =
408MHz PLLP0 divided by 68 for 6MHz, then a SD Clock Control register
divisor of 16 = 375KHz). But the resulting SD card clock, as measured by
the HW team, is 700KHz, which is out-of-spec. So the WAR is to use the
values given in the TRM PLLP table to generate a 400KHz SD-clock (CAR
clock of 24.7MHz, SD Clock Control divisor of 62) only for SDMMC1 on
T210 when the requested clock is
Reviewed-by: Jaehoon Chung -
As per the T210 TRM, when running at 3.3v, the SDMMC1 tap/trim and
autocal values need to be set to condition the signals correctly before
talking to the SD-card. This is the same as what's being done in CBoot,
but it gets reset when the SDMMC1 HW is soft-reset during SD driver
init, so needs to be repeated here. Also set autocal and tap/trim for
SDMMC3, although no T210 boards use it for SD-card at this time.Signed-off-by: Tom Warren
Reviewed-by: Jaehoon Chung
09 Mar, 2020
3 commits
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The 4 bit MMC controllers have an internal debounce for the SDCD line
with a debounce delay of 1 second. Therefore, after clocks to the IP are
enabled, software has to wait for this time before it can power on the
controller.Add a deferred_probe() callback which polls on sdcd for a maximum of 2 seconds
before switching on power to the controller or (in the case of no card)
returning a ENOMEDIUM. This pushes the 1 second wait time to when the
card is actually needed rather than at every probe() making sure that
users who don't insert an SD card in the slot don't have to wait such a
long time.Signed-off-by: Faiz Abbas
Signed-off-by: Lokesh Vutla -
With the latest RIOT, there is a different otap delay value for each
speed mode. Add a new binding with every supported speed mode. Also
disable a given speed mode in the host caps if its corresponding
otap-del-sel is not present.Signed-off-by: Faiz Abbas
Signed-off-by: Lokesh Vutla -
MMC_LEGACY & SD_LEGACY are not differentiated timings in the spec and
don't have any meaningful differences. Therefore, get rid of all
references to SD_LEGACY and use MMC_LEGACY to mean both of them.Signed-off-by: Faiz Abbas
Signed-off-by: Lokesh Vutla
