Eric Lee / smarc-uboot

23 Jul, 2013

1 commit

08 Jun, 2013

1 commit

  • 842033e69   pci: introduce CONFIG_PCI_INDIRECT_BRIDGE option ... Browse Code »

    The pci_indirect.c file is always compiled when
    CONFIG_PCI is defined although the indirect PCI
    bridge support is not needed by every board.

    Introduce a new CONFIG_PCI_INDIRECT_BRIDGE
    config option and only compile indirect PCI
    bridge support if this options is enabled.

    Also add the new option into the configuration
    files of the boards which needs that.

    Compile tested for powerpc, x86, arm and nds32.
    MAKEALL results:

    powerpc:
    --------------------- SUMMARY ----------------------------
    Boards compiled: 641
    Boards with warnings but no errors: 2 ( ELPPC MPC8323ERDB )
    ----------------------------------------------------------
    Note: the warnings for ELPPC and MPC8323ERDB are present even
    without the actual patch.

    x86:
    --------------------- SUMMARY ----------------------------
    Boards compiled: 1
    ----------------------------------------------------------

    arm:
    --------------------- SUMMARY ----------------------------
    Boards compiled: 311
    ----------------------------------------------------------

    nds32:
    --------------------- SUMMARY ----------------------------
    Boards compiled: 3
    ----------------------------------------------------------

    Cc: Tom Rini
    Cc: Daniel Schwierzeck
    Signed-off-by: Gabor Juhos

    Gabor Juhos
     

27 Jan, 2012

1 commit

  • 25efd99db   nand_spl: store ecc data on the stack ... Browse Code »

    Adapt the following patch from spl to nand_spl:

    Author: Stefano Babic
    Date: Thu Dec 15 10:55:37 2011 +0100

    nand_spl_simple: store ecc data on the stack

    Currently nand_spl_simple puts it's temp data at 0x10000 offset in SDRAM
    which is likely to contain already loaded data.
    The patch saves the oob data and the ecc on the stack replacing
    the fixed address in RAM.

    Signed-off-by: Stefano Babic
    CC: Ilya Yanok
    CC: Scott Wood
    CC: Tom Rini
    CC: Simon Schwarz
    CC: Wolfgang Denk
    Signed-off-by: Scott Wood

    While nand_spl is on its way out, in favor of spl, there are still
    many boards using it, and conversions are gradual. This allows us
    to get rid of CONFIG_SYS_NAND_ECCSTEPS and CONFIG_SYS_NAND_ECCTOTAL now,
    which would otherwise be likely to linger unreferenced after a conversion.

    It also eliminates a temporary error in the hawkboard_nand build, since
    the spl version of the patch removed ECCSTEPS/TOTAL from hawkboard.h, but
    the spl conversion is pending (and may be merged via a different tree).

    Signed-off-by: Scott Wood

    Scott Wood
     

27 Oct, 2010

2 commits

  • 25ddd1fb0   Replace CONFIG_SYS_GBL_DATA_SIZE by auto-generated value ... Browse Code »

    CONFIG_SYS_GBL_DATA_SIZE has always been just a bad workarond for not
    being able to use "sizeof(struct global_data)" in assembler files.
    Recent experience has shown that manual synchronization is not
    reliable enough. This patch renames CONFIG_SYS_GBL_DATA_SIZE into
    GENERATED_GBL_DATA_SIZE which gets automatically generated by the
    asm-offsets tool. In the result, all definitions of this value can be
    deleted from the board config files. We have to make sure that all
    files that reference such data include the new file.

    No other changes have been done yet, but it is obvious that similar
    changes / simplifications can be done for other, related macro
    definitions as well.

    Signed-off-by: Wolfgang Denk
    Acked-by: Kumar Gala

    Wolfgang Denk
     
  • 553f09823   Rename CONFIG_SYS_INIT_RAM_END into CONFIG_SYS_INIT_RAM_SIZE ... Browse Code »

    CONFIG_SYS_INIT_RAM_END was a misnomer as it suggests this might be
    some end address; to make the meaning more clear we rename it into
    CONFIG_SYS_INIT_RAM_SIZE

    No other code changes are performed in this patch, only minor editing
    of white space (due to the changed length) and the comments was done,
    where noticed.

    Note that the code for the PATI and cmi_mpc5xx board configurations
    looks seriously broken. Last known maintainers on Cc:

    Signed-off-by: Wolfgang Denk
    Cc: Denis Peter
    Cc: Martin Winistoerfer
    Acked-by: Kumar Gala

    Wolfgang Denk
     

19 Oct, 2010

1 commit

23 Sep, 2010

1 commit

  • 550650ddd   ppc4xx: Use common NS16550 driver for PPC4xx UART ... Browse Code »

    This patch removes the PPC4xx UART driver. Instead the common NS16550
    driver is used, since all PPC4xx SoC's use this peripheral device.

    The file 4xx_uart.c now only implements the UART clock calculation
    function which also sets the SoC internal UART divisors.

    All PPC4xx board config headers are changed to use this common NS16550
    driver now.

    Tested on these boards:
    acadia, canyonlands, katmai, kilauea, sequoia, zeus

    Signed-off-by: Stefan Roese

    Stefan Roese
     

20 Sep, 2010

1 commit

  • bf5608076   4xx: add missing CONFIG_SYS_SRAM_SIZE definition ... Browse Code »

    A number of boards define CONFIG_SYS_SRAM_BASE but fail to define
    CONFIG_SYS_SRAM_SIZE which is needed when cleaning up the code that
    prints this information with the bdinfo command.

    Add the missing deinitions.

    Signed-off-by: Wolfgang Denk
    Cc: Stefan Roese
    Acked-by: Stefan Roese

    Wolfgang Denk
     

23 Jul, 2010

1 commit

09 Nov, 2009

1 commit

  • 916ed9444   ppc4xx: Canyonlands: Change EBC bus config to drive always (no high-z) ... Browse Code »

    This patch fixes a problem only seen very occasionally on Canyonlands.
    The NOR flash interface (CFI driver) doesn't work reliably in all cases.
    Erasing and/or programming sometimes doesn't work. Sometimes with
    an error message, like "flash not erased" when trying to program an
    area that should have just been erased. And sometimes without any error
    messages. As mentioned above, this problem was only seen rarely and with
    some PLL configuration (CPU speed, EBC speed).

    Now I spotted this problem a few times, when running my Canyonlands with
    the following setup (chip_config):

    1000-nor - NOR CPU:1000 PLB: 200 OPB: 100 EBC: 100

    Changing the EBC configuration to not release the bus into high
    impedance state inbetween the transfers (ATC, DTC and CTC bits set to 1
    in EBC0_CFG) seems to fix this problem. I haven't seen any failure
    anymore with this patch applied.

    Signed-off-by: Stefan Roese
    Cc: David Mitchell
    Cc: Jeff Mann

    Stefan Roese
     

18 Aug, 2009

1 commit

  • 514bab660   ppc4xx: Fix "chip_config" command for AMCC Arches ... Browse Code »

    This patch fixes the "chip_config" command for I2C bootstrap EEPROM
    configuration. First it changes the I2C bootstrap EEPROM address to
    0x54 as this is used on Arches (instead of 0x52 on Canyonlands/
    Glacier). Additionally, the NAND bootstrap settings are removed
    for Arches since Arches doesn't support NAND-booting.

    Signed-off-by: Stefan Roese

    Stefan Roese
     

24 Jul, 2009

1 commit

  • 87c0b7290   Add "chip_config" command for PPC4xx bootstrap configuration ... Browse Code »

    This patch adds a generic command for programming I2C bootstrap
    eeproms on PPC4xx. An implementation for Canyonlands board is
    included.

    The command name is intentionally chosen not to be PPC4xx specific.
    This way other CPU's/SoC's can implement a similar command under
    the same name, perhaps with a different syntax.

    Usage on Canyonlands:

    => chip_config
    Available configurations (I2C address 0x52):
    600-nor - NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100
    600-nand - NAND CPU: 600 PLB: 200 OPB: 100 EBC: 100
    800-nor - NOR CPU: 800 PLB: 200 OPB: 100 EBC: 100
    800-nand - NAND CPU: 800 PLB: 200 OPB: 100 EBC: 100
    1000-nor - NOR CPU:1000 PLB: 200 OPB: 100 EBC: 100
    1000-nand - NAND CPU:1000 PLB: 200 OPB: 100 EBC: 100
    1066-nor - NOR CPU:1066 PLB: 266 OPB: 88 EBC: 88 ***
    1066-nand - NAND CPU:1066 PLB: 266 OPB: 88 EBC: 88
    => chip_config 600-nor
    Using configuration:
    600-nor - NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100
    done (dump via 'i2c md 52 0.1 10')
    Reset the board for the changes to take effect

    Other 4xx boards will be migrated to use this command soon
    as well.

    Signed-off-by: Stefan Roese
    Signed-off-by: Dirk Eibach
    Acked-by: Matthias Fuchs

    Stefan Roese
     

19 Jul, 2009

1 commit

  • e405afab1   Canyonlands SATA harddisk driver ... Browse Code »

    This patch adds a SATA harddisk driver for the canyonlands.
    This patch is kernel driver's porting.
    This patch corresponded to not cmd_scsi but cmd_sata.
    This patch divided an unused member with ifndef __U_BOOT__ in the structure.

    [environment variable, boot script]
    setenv bootargs root=/dev/sda7 rw
    setenv bootargs ${bootargs} console=ttyS0,115200
    ext2load sata 0:2 0x400000 /canyonlands/uImage
    ext2load sata 0:2 0x800000 /canyonlands/canyonlands.dtb
    fdt addr 0x800000 0x4000
    bootm 0x400000 - 0x800000

    If you drive SATA-2 disk on Canyonlands, you must change parts from
    PI2PCIE212 to PI2PCIE2212 on U25. We confirmed to boot by using
    following disks:

    1.Vendor: Fujitsu Type: MHW2040BS
    2.Vendor: Fujitsu Type: MHW2060BK
    3.Vendor: HAGIWARA SYS-COM:HFD25S-032GT
    4.Vendor: WesternDigital Type: WD3200BJKT (CONFIG_LBA48 required)
    5.Vendor: WesternDigital Type: WD3200BEVT (CONFIG_LBA48 required)
    6.Vendor: Hitachi Type: HTS543232L9A300 (CONFIG_LBA48 required)
    7.Vendor: Seagate Type: ST31000333AS (CONFIG_LBA48 required)
    8.Vendor: Transcend Type: TS32GSSD25S-M
    9.Vendor: MTRON Type: MSD-SATA1525-016

    Signed-off-by: Kazuaki Ichinohe

    Kazuaki Ichinohe
     

08 Jul, 2009

1 commit

  • 26d37f006   ppc4xx: Fix FDT EBC mappings on Canyonlands ... Browse Code »

    This patch fixes 2 problems with FDT EBC mappings on Canyonlands.
    First, NAND EBC mapping was missing, making Linux NAND driver
    unusable on this board. Second, NOR remapping code assumed that
    NOR is always on CS0, however when booting from NAND NOR is on CS3.

    Signed-off-by: Felix Radensky
    Signed-off-by: Stefan Roese

    Felix Radensky
     

24 Jan, 2009

1 commit

  • 6c869637f   NAND: rename NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPS ... Browse Code »

    This patch renames NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPS and
    changes the default from 8 to 1 for the legacy and the new MTD
    NAND layer. This allows to remove all NAND_MAX_CHIPS definitions
    in the board config files because none of the boards use multi
    chip support (NAND_MAX_CHIPS > 1) so far. The bamboo and the DU440
    define

    #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE

    but that's bogus and did not work anyhow.

    Signed-off-by: Wolfgang Grandegger
    Signed-off-by: Scott Wood

    Wolfgang Grandegger
     

21 Nov, 2008

1 commit

  • ddf45cc75   ppc4xx: Changed 460EX/GT OCM TLB and internal SRAM initialization ... Browse Code »

    Expanded OCM TLB to allow access to 64K OCM as well as 256K of
    internal SRAM.

    Adjusted internal SRAM initialization to match updated user
    manual recommendation.

    OCM & ISRAM are now mapped as follows:
    physical virtual size
    ISRAM 0x4_0000_0000 0xE300_0000 256k
    OCM 0x4_0004_0000 0xE304_0000 64k

    A single TLB was used for this mapping.

    Signed-off-by: Dave Mitchell
    Signed-off-by: Stefan Roese

    Dave Mitchell
     

31 Oct, 2008

1 commit

21 Oct, 2008

1 commit

  • f09f09d38   ppc4xx: Add AMCC Arches board support (dual 460GT) ... Browse Code »

    The Arches Evaluation board is based on the AMCC 460GT SoC chip.
    This board is a dual processor board with each processor providing
    independent resources for Rapid IO, Gigabit Ethernet, and serial
    communications. Each 460GT has it's own 512MB DDR2 memory, 32MB NOR
    FLASH, UART, EEPROM and temperature sensor, along with a shared debug
    port. The two 460GT's will communicate with each other via shared
    memory, Gigabit Ethernet and x1 PCI-Express.

    Signed-off-by: Adam Graham
    Signed-off-by: Victor Gallardo
    Signed-off-by: Stefan Roese

    Adam Graham
     

19 Oct, 2008

1 commit

14 Oct, 2008

1 commit

11 Sep, 2008

3 commits

13 Aug, 2008

1 commit

06 Jun, 2008

1 commit

  • 490f20409   ppc4xx: Unify AMCC's board config files (part 2/3) ... Browse Code »

    This patch series unifies the AMCC eval board ports by introducing
    a common include header for all AMCC eval boards:

    include/configs/amcc-common.h

    This header now includes all common configuration options/defines which
    are removed from the board specific headers.

    The reason for this is ease of maintenance and unified look and feel
    of all AMCC boards.

    Signed-off-by: Stefan Roese

    Stefan Roese
     

22 Apr, 2008

1 commit

  • 5d40d4430   ppc4xx: Fix Canyonlands and Glacier default environment for fdt usage ... Browse Code »

    This patch fixes the Canyonlands and Glacier default environment to better
    fit to the arch/powerpc device-tree kernels. The variables dealing with
    arch/ppc booting are removed, since these boards are supported only in
    arch/powerpc. Glacier uses the same config file as Canyonlands.

    Also, the Glacier now uses non-FPU rootpath, since 460GT has no FPU.

    Signed-off-by: Stefan Roese

    Stefan Roese
     

18 Apr, 2008

1 commit

09 Apr, 2008

1 commit

28 Mar, 2008

1 commit

27 Mar, 2008

1 commit

  • 4c9e85573   ppc4xx: Add AMCC Glacier 406GT eval board support ... Browse Code »

    This patch adds support for the AMCC Glacier 460GT eval board.
    The main difference to the Canyonlands board are listed here:

    - 4 ethernet ports instead of 2
    - no SATA port
    - no USB port

    Currently EMAC2+3 are not working. This will be fixed in a later
    release.

    Signed-off-by: Stefan Roese

    Stefan Roese
     

15 Mar, 2008

3 commits