21 Sep, 2017

2 commits


19 Sep, 2017

2 commits


15 Sep, 2017

1 commit

  • All these places seem to inherit the codes from the MMC driver where
    a FIXME was put in the comment. However the correct operation after
    read should be cache invalidate, not flush.

    The underlying drivers should be responsible for the cache operation.
    Remove these codes completely.

    Signed-off-by: Bin Meng
    Reviewed-by: Stefan Roese
    Reviewed-by: York Sun
    Reviewed-by: Joe Hershberger
    Reviewed-by: Simon Glass
    Tested-by: York Sun

    Bin Meng
     

11 Sep, 2017

3 commits

  • This patch adds support for RGMII protocol

    NXP's LDPAA2 support RGMII protocol. LS1088A is the
    first Soc supporting both RGMII and SGMII.

    Signed-off-by: Prabhakar Kushwaha
    Signed-off-by: Amrita Kumari
    Signed-off-by: Ashish Kumar
    Reviewed-by: York Sun

    Ashish Kumar
     
  • LS1088A is compliant with the Layerscape Chassis Generation 3 with
    eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
    SDRAM memory controller with ECC, Data path acceleration architecture
    2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
    QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.

    Signed-off-by: Alison Wang
    Signed-off-by: Prabhakar Kushwaha
    Signed-off-by: Ashish Kumar
    Signed-off-by: Raghav Dogra
    Signed-off-by: Shaohui Xie
    [YS: Revised commit message]
    Reviewed-by: York Sun

    Ashish Kumar
     
  • Update MC address calculation as per MC design requirement of address
    as least significant 512MB address of MC private allocated memory,
    i.e. address should point to end address masked with 512MB offset in
    private DRAM block.

    Signed-off-by: Priyanka Jain
    Signed-off-by: Ashish Kumar
    [YS: reformatted commit message]
    Reviewed-by: York Sun

    Priyanka Jain
     

08 Sep, 2017

2 commits

  • %s/Desriptor/Descriptor/g

    Signed-off-by: Heinrich Schuchardt
    Acked-by: Joe Hershberger

    Heinrich Schuchardt
     
  • The old logic always enabled the TX-delay when the phy-mode was set to
    PHY_INTERFACE_MODE_RGMII. With this patch we enable the TX delay for
    PHY_INTERFACE_MODE_RGMII_ID and PHY_INTERFACE_MODE_RGMII_TXID and
    disable it for PHY_INTERFACE_MODE_RGMII.

    Based on a similar change made in the Linux Realtek PHY driver
    by Martin Blumenstingl .

    Signed-off-by: Madalin Bucur
    Acked-by: Joe Hershberger
    Acked-by: York Sun

    Madalin Bucur
     

17 Aug, 2017

1 commit


16 Aug, 2017

6 commits


15 Aug, 2017

2 commits


13 Aug, 2017

1 commit

  • The GMAC in the RK3368 once again is identical to the incarnation in
    the RK3288 and the RK3399, except for where some of the configuration
    and control registers are located in the GRF.

    This adds the RK3368-specific logic necessary to reuse this driver.

    Signed-off-by: Philipp Tomsich
    Reviewed-by: Simon Glass
    Acked-by: Joe Hershberger

    Philipp Tomsich
     

11 Aug, 2017

1 commit


10 Aug, 2017

11 commits

  • Set BM poll size once during priv probe and do not
    overwrite it during port probe procedure. Pool is common for
    all CP ports.

    Signed-off-by: Stefan Chulski
    Tested-by: iSoC Platform CI
    Reviewed-by: Nadav Haklai
    Reviewed-by: Igal Liberman
    Acked-by: Joe Hershberger
    Signed-off-by: Stefan Roese

    Stefan Chulski
     
  • TX drain in transmit procedure could cause issues due
    to race between drain procedure and transmition of descriptor
    between AGGR TXQ and physical TXQ.
    TXQ will be cleared before moving to Linux by stop procedure.

    Signed-off-by: Stefan Chulski
    Tested-by: iSoC Platform CI
    Reviewed-by: Nadav Haklai
    Reviewed-by: Igal Liberman
    Acked-by: Joe Hershberger
    Signed-off-by: Stefan Roese

    Stefan Chulski
     
  • MVPP22 driver support 64 Bit arch and require BM pool
    high address configuration.

    Signed-off-by: Stefan Chulski
    Tested-by: iSoC Platform CI
    Reviewed-by: Nadav Haklai
    Reviewed-by: Igal Liberman
    Acked-by: Joe Hershberger
    Signed-off-by: Stefan Roese

    Stefan Chulski
     
  • Remove IRQ configuration from U-Boot PP driver.
    U-Boot don't use interrupts and configuration of IRQ in U-Boot
    caused crashes in Linux shared interrupt mode.
    Also interrupt use is redundant in RX routine since a single RX
    queue is used.

    Signed-off-by: Stefan Chulski
    Tested-by: iSoC Platform CI
    Reviewed-by: Nadav Haklai
    Reviewed-by: Igal Liberman
    Acked-by: Joe Hershberger
    Signed-off-by: Stefan Roese

    Stefan Chulski
     
  • MBUS driver were replaced by AXI in PPv22 and relevant
    only for PPv21.

    Signed-off-by: Stefan Chulski
    Tested-by: iSoC Platform CI
    Reviewed-by: Nadav Haklai
    Reviewed-by: Igal Liberman
    Acked-by: Joe Hershberger
    Signed-off-by: Stefan Roese

    Stefan Chulski
     
  • U-boot use single physical tx queue with size 16 descriptors.
    So aggregated tx queue size should be equal to physical tx queue
    and cpu descriptor chunk(number of descriptors delivered from
    physical tx queue to aggregated tx queue by one chunk) shouldn't be
    larger than physical tx queue.

    Fix:
    Set AGGR_TXQ and CPU_DESC_CHUNK to be 16 descriptors, same as
    physical TXQ.

    Signed-off-by: Stefan Chulski
    Tested-by: iSoC Platform CI
    Reviewed-by: Nadav Haklai
    Reviewed-by: Igal Liberman
    Acked-by: Joe Hershberger
    Signed-off-by: Stefan Roese

    Stefan Chulski
     
  • Issue:
    BM counters were overrun by probe that called per Network interface and
    caused release of wrong number of buffers during remove procedure.

    Fix:
    Use probe_done and num_ports to call init and remove procedure
    once per communication controller.

    Signed-off-by: Stefan Chulski
    Tested-by: iSoC Platform CI
    Reviewed-by: Igal Liberman
    Acked-by: Joe Hershberger
    Signed-off-by: Stefan Roese

    Stefan Chulski
     
  • This patch enables padding of packets shorter than 64B in TX(set by default).
    Disabling of padding causes crashes on MACCIATO board.

    Signed-off-by: Stefan Chulski
    Tested-by: iSoC Platform CI
    Reviewed-by: Igal Liberman
    Acked-by: Joe Hershberger
    Signed-off-by: Stefan Roese

    Stefan Chulski
     
  • A8K marvell SoC has two South Bridge communication controllers(CP0 and CP1).
    Each communication controller has packet processor ports and MDIO.
    On MACHIATOBin board ports from CP1 are connected to mdio on CP0.

    Issue:
    Wrong base address is assigned to MDIO interface during probe.

    Fix:
    Get MDIO address from PHY handler parent base address.

    This should be refined in the future when MDIO driver is implemented.

    Signed-off-by: Stefan Chulski
    Tested-by: iSoC Platform CI
    Reviewed-by: Igal Liberman
    Acked-by: Joe Hershberger
    Signed-off-by: Stefan Roese

    Stefan Chulski
     
  • This patch add GPIO configuration support in mvpp2x driver.
    Driver will handle 10G SFP gpio reset and SFP TX disable. GPIO pins should
    be set in device tree.

    Signed-off-by: Stefan Chulski
    Tested-by: iSoC Platform CI
    Reviewed-by: Kostya Porotchkin
    Reviewed-by: Igal Liberman
    Acked-by: Joe Hershberger
    Signed-off-by: Stefan Roese

    Stefan Chulski
     
  • In fsl_mc_ldpaa_exit(), in case of mc is booted and dpl is applied,
    it should return earlier without executing dpbp_exit().

    Signed-off-by: Santan Kumar
    Acked-by: Priyanka Jain
    Acked-by: Yogesh Narayan Gaur
    Reviewed-by: York Sun

    Santan Kumar
     

08 Aug, 2017

8 commits