05 Aug, 2015
5 commits
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USB-related options are usually prefixed with CONFIG_USB and platform-specific
adaptation for the MUSB controller already have a CONFIG_USB_MUSB prefix, so
this switches all MUSB-related options to a CONFIG_USB_MUSB prefix, for
consistency.Signed-off-by: Paul Kocialkowski
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There is no particular reason why the USB Kconfig option should be specific to
host mode. In prevision of adding MUSB host and gadget to Kconfig, this moves
the title and help message of the USB Kconfig option to a more generic format.Adding comments to the usb Kconfig allows for a better separation and more
readability in generated configs and in menuconfig.Signed-off-by: Paul Kocialkowski
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The USB_ARCH_HAS_HCD currently serves no purpose and adds some confusion to the
required Kconfig options that are required to have USB support.Dropping it makes things easier and doesn't break anything, since it was unused
anyways.Signed-off-by: Paul Kocialkowski
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This patch makes the dwc2 controller like ehci / ohci / xhci controllers
by calling the board_usb_init() function from usb_lowlevel_init.This can then be implemented by specific platforms to initialise
their USB hardware (phys / clocks etc).Signed-off-by: Peter Griffin
04 Aug, 2015
24 commits
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This patch replaces not existing addr_uboot environment variable by
loadaddr at get_uboot_net and burn_uboot_xxx commands. Otherwise these
commands are broken.Signed-off-by: Vitaly Andrianov
Acked-by: Nishanth Menon -
Add USB XHCI support for ls2085rdb platform
Signed-off-by: Nikhil Badola
Reviewed-by: York Sun -
Add USB XHCI support for ls2085qds platform
Signed-off-by: Nikhil Badola
Reviewed-by: York Sun -
Define base address of both usb xhci controllers in lsch3 config
in the format (IMMR + offset) for LS2085ASigned-off-by: Nikhil Badola
Reviewed-by: York Sun -
Define CONFIG_SYS_CACHELINE_SIZE for LS2085A which is required by
USB XHCI stack for alignmentSigned-off-by: Nikhil Badola
Reviewed-by: York Sun -
By default the bstopre value has been set to 0x100, used to be 1/4
value of refint. Modern DDR has increased the refresh time. Adjust
to 1/4 of refresh interval dynamically. Individual board can still
override this value in board ddr file, or to use auto-precharge.Signed-off-by: York Sun
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Signed-off-by: Horia Geantă
Acked-by: Ruchika Gupta
Reviewed-by: York Sun -
HW coherency won't work properly for CAAM write transactions
if AWCACHE is left to default (POR) value - 4'b0001.
It has to be programmed to 4'b0010.For platforms that have HW coherency support:
-PPC-based: the update has no effect; CAAM coherency already works
due to the IOMMU (PAMU) driver setting the correct memory coherency
attributes
-ARM-based: the update fixes cache coherency issues,
since IOMMU (SMMU) driver is not programmed to behave similar to PAMUFixes: b9eebfade974c ("fsl_sec: Add hardware accelerated SHA256 and SHA1")
Signed-off-by: Horia Geantă
Reviewed-by: Aneesh Bansal
Reviewed-by: Mingkai Hu
Acked-by: Ruchika Gupta
Reviewed-by: York Sun -
Use fdt_setprop_u32() instead of fdt_setprop().
Fixes: 0181937fa371a ("crypto/fsl: Add fixup for crypto node")
Signed-off-by: Horia Geantă
Reviewed-by: Mingkai Hu
Acked-by: Ruchika Gupta
Reviewed-by: York Sun -
The patch will initialize PCIe controller on EP mode
1. Setup bar:
bar0 32bit 4K for specific configuration
bar1 32bit 8K for MSIX
bar2 64bit 4K for descriptor of memory
bar4 64bit 1M for DMA memory test
2. Setup iATU:
iATU inbound 0-3 to map bar transaction to memory address
started at CONFIG_SYS_PCI_EP_MEMORY_BASE
iATU outbound 0 to map 4G memory spaceSigned-off-by: Minghuan Lian
Reviewed-by: York Sun -
PCIe extends device's configuration space to 4k and provides
extended capability. The patch adds function to find them.
The code is ported from Linux PCIe driver.Signed-off-by: Minghuan Lian
Reviewed-by: Bin Meng
Reviewed-by: York Sun -
MC firware version 8.0.0 contains new command flags. This patch
contains modifications in FLIB files to support the new command flags.Signed-off-by: Itai Katz
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
The sampling of the oscillator can be done in multiple modes for
generating the entropy value. By default, this is set to von
Neumann. This patch changes the sampling to raw data, since it
has been discovered that the generated entropy has a better
'quality'.Signed-off-by: Alex Porosanu
Acked-by: Ruchika Gupta
Reviewed-by: York Sun -
The entropy delay (the length in system clocks of each
entropy sample) for the RNG4 block of CAAM is dependent
on the frequency of the SoC. By elaborate methods, it
has been determined that a good starting value for all
platforms integrating the CAAM IP is 3200. Using a
higher value has additional benefit of speeding up
the process of instantiating the RNG, since the entropy
delay will be increased and instantiation of the RNG
state handles will be reattempted by the driver. If the
starting value is low, for certain platforms, this can
lead to a quite lengthy process.
This patch changes the starting value of the length of
the entropy sample to 3200 system clocks.
In addition to this change, the attempted entropy delay
values are now printed on the console upon initialization
of the RNG block.Signed-off-by: Alex Porosanu
Acked-by: Ruchika Gupta
Reviewed-by: York Sun -
The rtfrqmax & rtfrqmin set the bounds of the expected frequency of the
oscillator, when SEC runs at its maximum frequency. For certain platforms
(f.i. T2080), the oscillator is very fast and thus if the SEC runs at
a lower than normal frequency, the ring oscillator is incorrectly detected
as being out of bounds.This patch effectively disables the maximum frequency check, by setting a
high enough maximum allowable frequency for the oscillator. The reasoning
behind this is that usually a broken oscillator will run too slow
(i.e. not run at all) rather than run too fast.Signed-off-by: Alex Porosanu
Acked-by: Ruchika Gupta
Reviewed-by: York Sun -
To improve eTSEC performance on LS1021A Rev2.0,
snooping of all transmit frames from memory and
all transmit BD memory accesses in enabled.Signed-off-by: Alison Wang
Reviewed-by: York Sun -
On LS1021A Rev2.0, OCRAM's security level needs to be changed to
non-secure access for SD boot. This patch will allow OCRAM
access permission as R/W in SPL.Signed-off-by: Alison Wang
Reviewed-by: York Sun -
Bootrom will put cpus into WFE state when boot cpu release cpus, so
target cpu cannot correctly go to spin state.Add 'sev' to wakeup non-boot cpu that hold on bootrom space, let target
cpu can fall into u-boot spin table.Signed-off-by: Wang Dongsheng
Reviewed-by: York Sun -
Program the external regulator to switch off voltage in deep sleep.
Signed-off-by: Chenhui Zhao
Acked-by: Alison Wang
Reviewed-by: York Sun -
Signed-off-by: Tang Yuantian
Acked-by: Alison Wang
Reviewed-by: York Sun -
Enable bootscript support in secure boot for establishing
chain of trust on LS1021atwr.Signed-off-by: Gaurav Rana
Reviewed-by: York Sun -
strncpy is safer than strcpy, use it to instead of strcpy.
Signed-off-by: Zhao Qiang
Reviewed-by: York Sun -
when using printf, the parameter type need to be compatible
type, so transform them to compatible typeSigned-off-by: Zhao Qiang
Reviewed-by: York Sun -
For ls1021a, Reserve secure code in to memory in case OCRAM
is needed by other usage.Signed-off-by: Zhuoyu Zhang
Acked-by: Alison Wang
Reviewed-by: York Sun
03 Aug, 2015
1 commit
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Signed-off-by: Tom Rini
02 Aug, 2015
10 commits
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This function is called from esdhc_send_cmd so we need it available to
everyone.Signed-off-by: Tom Rini
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Fix:
undefined reference to `spi_flash_free'
undefined reference to `spi_flash_probe'Signed-off-by: Stefano Babic
CC: Stefan Roese
Cc: Markus Niebel
Acked-by: Stefan Roese -
1. Add USDHC, I2C, UART, 74LV, USB, QSPI support.
2. Support SPL
3. CONFIG_MX6UL_14X14_EVK_EMMC_REWORK is introduced, this board default
supports sd for usdhc2, but can do hardware rework to make usdhc2 support
emmc.Boot Log:
U-Boot SPL 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59)
reading u-boot.img
reading u-boot.imgU-Boot 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59 +0800)
CPU: Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz)
CPU: Commercial temperature grade (0C to 95C)CPU: Thermal invalid data, fuse: 0x0
- invalid sensor device
Reset cause: POR
Board: MX6UL 14x14 EVK
I2C: ready
DRAM: 512 MiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1
*** Warning - bad CRC, using default environmentIn: serial
Out: serial
Err: serial
Net: CPU Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot: 0Signed-off-by: Peng Fan
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i.MX6UL's DRAM space starts from 0x80000000, same to i.MX6SX, so use
same address with i.MX6SX.Signed-off-by: Peng Fan
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1. Define two structures mx6ul_iomux_ddr_regs and mx6ul_iomux_grp_regs.
2. Add a new function mx6ul_dram_iocfg to configure dram io.
3. Refactor MMDC1 macro, discard "#ifdef CONFIG_MX6SX". Since
only mmdc0 channel exists on i.MX6SX/UL, redefine MMDC1 macro support
runtime check, but not hardcoding #ifdef macros.
4. Introduce mx6ul-ddr.h, which includes the register address for DRAM
IO configuration.Signed-off-by: Peng Fan
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DRAM space starts from 0x80000000 for i.MX6UL, so need to
fix LOADADDR, SYS_TEXT_BASE.Signed-off-by: Peng Fan
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i.MX6UL does not have GPIO6/7, so do not include them for i.MX6UL.
Signed-off-by: Peng Fan
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PAD_CTL_SPEED_LOW for i.MX6SX/UL is (0 << 6)
Signed-off-by: Ye.Li
Signed-off-by: Peng Fan -
1.Update WDOG settings.
2.No need to gate/ungate all PFDs for i.MX6UL.Signed-off-by: Peng Fan
Signed-off-by: Ye.Li
