Eric Lee / smarc-uboot

15 Oct, 2013

4 commits

14 Oct, 2013

2 commits

11 Oct, 2013

1 commit

10 Oct, 2013

2 commits

  • 99b4eaa68   usb: Prevent using reserved registers on DM36x usb ... Browse Code »

    The musb driver defines and uses MUSB_CSR0_H_DIS_PING, however this
    bit is reserved on the DM36x. Thus this patch ensures that the
    reserved bit is not accesssed.

    It has been observed that some USB devices will fail to enumerate
    with errors such as 'error in inquiry' without this patch.

    See http://www.ti.com/litv/pdf/sprufh9a for details.

    Cc: Marek Vasut
    Cc: Tom Rini
    Signed-off-by: Andrew Murray
    Acked-by: Marek Vasut

    Andrew Murray
     
  • 40462e541   mtd: driver _read() returns max_bitflips; mtd_read() returns -EUCLEAN ... Browse Code »

    Linux modified the MTD driver interface in commit edbc4540 (with the
    same name as this commit). The effect is that calls to mtd_read will
    not return -EUCLEAN if the number of ECC-corrected bit errors is below
    a certain threshold, which defaults to the strength of the ECC. This
    allows -EUCLEAN to stop indicating "some bits were corrected" and begin
    indicating "a large number of bits were corrected, the data held in
    this region of flash may be lost soon". UBI makes use of this and when
    -EUCLEAN is returned from mtd_read it will move data to another block
    of flash. Without adopting this interface change UBI on U-boot attempts
    to move data between blocks every time a single bit is corrected using
    the ECC, which is a very common occurance on some devices.

    For some devices where bit errors are common enough, UBI can get stuck
    constantly moving data around because each block it attempts to use has
    a single bit error. This condition is hit when wear_leveling_worker
    attempts to move data from one PEB to another in response to an
    -EUCLEAN/UBI_IO_BITFLIPS error. When this happens ubi_eba_copy_leb is
    called to perform the data copy, and after the data is written it is
    read back to check its validity. If that read returns UBI_IO_BITFLIPS
    (in response to an MTD -EUCLEAN) then ubi_eba_copy_leb returns 1 to
    wear_leveling worker, which then proceeds to schedule the destination
    PEB for erasure. This leads to erase_worker running on the PEB, and
    following a successful erase wear_leveling_worker is called which
    begins this whole cycle all over again. The end result is that (without
    UBI debug output enabled) the boot appears to simply hang whilst in
    reality U-boot busily works away at destroying a block of the NAND
    flash. Debug output from this situation:

    UBI DBG: ensure_wear_leveling: schedule scrubbing
    UBI DBG: wear_leveling_worker: scrub PEB 1027 to PEB 4083
    UBI DBG: ubi_io_read_vid_hdr: read VID header from PEB 1027
    UBI DBG: ubi_io_read: read 4096 bytes from PEB 1027:4096
    UBI DBG: ubi_eba_copy_leb: copy LEB 0:0, PEB 1027 to PEB 4083
    UBI DBG: ubi_eba_copy_leb: read 1040384 bytes of data
    UBI DBG: ubi_io_read: read 1040384 bytes from PEB 1027:8192
    UBI: fixable bit-flip detected at PEB 1027
    UBI DBG: ubi_io_write_vid_hdr: write VID header to PEB 4083
    UBI DBG: ubi_io_write: write 4096 bytes to PEB 4083:4096
    UBI DBG: ubi_io_read_vid_hdr: read VID header from PEB 4083
    UBI DBG: ubi_io_read: read 4096 bytes from PEB 4083:4096
    UBI DBG: ubi_io_write: write 4096 bytes to PEB 4083:8192
    UBI DBG: ubi_io_read: read 4096 bytes from PEB 4083:8192
    UBI: fixable bit-flip detected at PEB 4083
    UBI DBG: schedule_erase: schedule erasure of PEB 4083, EC 55, torture 0
    UBI DBG: erase_worker: erase PEB 4083 EC 55
    UBI DBG: sync_erase: erase PEB 4083, old EC 55
    UBI DBG: do_sync_erase: erase PEB 4083
    UBI DBG: sync_erase: erased PEB 4083, new EC 56
    UBI DBG: ubi_io_write_ec_hdr: write EC header to PEB 4083
    UBI DBG: ubi_io_write: write 4096 bytes to PEB 4083:0
    UBI DBG: ensure_wear_leveling: schedule scrubbing
    UBI DBG: wear_leveling_worker: scrub PEB 1027 to PEB 4083
    ...

    This patch adopts the interface change as in Linux commit edbc4540 in
    order to avoid such situations. Given that none of the drivers under
    drivers/mtd return -EUCLEAN, this should only affect those using
    software ECC. I have tested that it works on a board which is
    currently out of tree, but which I hope to be able to begin
    upstreaming soon.

    Signed-off-by: Paul Burton
    Acked-by: Stefan Roese

    Paul Burton
     

08 Oct, 2013

5 commits

  • 9f3fe6da2   Merge branch 'master' of git://git.denx.de/u-boot-arm Browse Code »
    Tom Rini
     
  • 968294bd7   Merge branch 'master' of git://git.denx.de/u-boot-spi Browse Code »
    Tom Rini
     
  • c4a796329   spi: exynos: Support word transfers ... Browse Code »

    Since SPI register access is so expensive, it is worth transferring data
    a word at a time if we can. This complicates the driver unfortunately.

    Use the byte-swapping feature to avoid having to convert to/from big
    endian in software.

    This change increases speed from about 2MB/s to about 4.5MB/s.

    Signed-off-by: Simon Glass
    Signed-off-by: Rajeshwari S Shinde
    Reviewed-by: Jagannadha Sutradharudu Teki

    Rajeshwari Shinde
     
  • 120af1572   spi: exynos: Minimise access to SPI FIFO level ... Browse Code »

    Accessing SPI registers is slow, but access to the FIFO level register
    in particular seems to be extraordinarily expensive (I measure up to
    600ns). Perhaps it is required to synchronise with the SPI byte output
    logic which might run at 1/8th of the 40MHz SPI speed (just a guess).

    Reduce access to this register by filling up and emptying FIFOs
    more completely, rather than just one word each time around the inner
    loop.

    Since the rxfifo value will now likely be much greater that what we read
    before we fill the txfifo, we only fill the txfifo halfway. This is
    because if the txfifo is empty, but the rxfifo has data in it, then writing
    too much data to the txfifo may overflow the rxfifo as data arrives.

    This speeds up SPI flash reading from about 1MB/s to about 2MB/s on snow.

    Signed-off-by: Simon Glass
    Signed-off-by: Rajeshwari S Shinde
    Reviewed-by: Jagannadha Sutradharudu Teki

    Rajeshwari Shinde
     
  • 8d203afdd   spi: exynos: Support a delay after deactivate ... Browse Code »

    For devices that need some time to react after a spi transaction
    finishes, add the ability to set a delay.

    Implement this as a delay on the first/next transaction to avoid
    any delay in the fairly common case where a SPI transaction is
    followed by other processing.

    Signed-off-by: Simon Glass
    Signed-off-by: Rajeshwari S Shinde
    Reviewed-by: Jagannadha Sutradharudu Teki

    Rajeshwari Shinde
     

07 Oct, 2013

26 commits