08 Mar, 2014
2 commits
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USB spec says that the minimum disconnect threshold should be
over 525 mV. However, internal USB PHY threshold value is below
this specified value. Due to this some devices disconnect at
run-time. Hence, phy settings are tweaked to increased disconnect
threshold to be above 525mV by using this workaround.Signed-off-by: Suresh Gupta
Reviewed-by: York Sun -
SerDes PLLs may not lock reliably at 5 G VCO configuration(A006384)
and at cold temperatures(A006475), workaround recalibrate the
PLLs with some SerDes configurationBoth these errata are only applicable for b4 rev1.
So, make workaround for these errata conditional,
depending upon soc version.Signed-off-by: Shaveta Leekha
Reviewed-by: York Sun
22 Jan, 2014
1 commit
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Unfortunately a typo presents "DDR-A003473" instead of "DDR-A003474".
Signed-off-by: York Sun
17 Oct, 2013
1 commit
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Erratum A006379 says CPCHDBCR0 bit field [10:14] has incorrect default
value after POR. The workaround is to set this field before enabling
CPC to 0x1e.Erratum A006379 applies to
T4240 rev 1.0
B4860 rev 1.0, 2.0Signed-off-by: York Sun
11 Sep, 2013
1 commit
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In a very rare condition, a system hang is possible when the e500 core
initiates a guarded load to PCI / PCIe /SRIO performs a coherent write
to memory. Please refer to errata document for more details. This erratum
applies to the following SoCs and their variants, if any.BSC9132
BSC9131
MPC8536
MPC8544
MPC8548
MPC8569
MPC8572
P1010
P1020
P1021
P1022
P1023
P2020
C29xSigned-off-by: York Sun
CC: Scott Wood
22 Aug, 2013
1 commit
21 Aug, 2013
1 commit
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Multiple read/write transactions initiated by security
engine may cause system to hang.
Workaround: set MCFGR[AXIPIPE] to 0 to avoid hang.Signed-off-by: Shengzhou Liu
Acked-by: York Sun
20 Aug, 2013
1 commit
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This workaround is for the erratum I2C A004447. Device reference
manual provides a scheme that allows the I2C master controller
to generate nine SCL pulses, which enable an I2C slave device
that held SDA low to release SDA. However, due to this erratum,
this scheme no longer works. In addition, when I2C is used as
a source of the PBL, the state machine is not able to recover.At the same time, delete the reduplicative definition of SVR_VER
and SVR_REV. The SVR_REV is the low 8 bits rather than the low 16
bits of svr. And we use the CONFIG_SYS_FSL_A004447_SVR_REV macro
instead of hard-code value 0x10, 0x11 and 0x20.The CONFIG_SYS_FSL_A004447_SVR_REV = 0x00 represents that one
version of platform has this I2C errata. So enable this errata
by IS_SVR_REV(svr, maj, min) function.Signed-off-by: Zhao Chenhui
Signed-off-by: Chunhe Lan
Cc: Scott Wood
Cc: Heiko Schocher
10 Aug, 2013
1 commit
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Erratum A-005812 Incorrect reservation clearing in Write Shadow mode can
result in invalid atomic operations. For u-boot, this erratum only impacts
SoCs running in write shadow mode.Signed-off-by: York Sun
24 Jul, 2013
1 commit
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Signed-off-by: Wolfgang Denk
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini
21 Jun, 2013
1 commit
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Erratum A-006593 is "Atomic store may report failure but still allow
the store data to be visible".The workaround is: "Set CoreNet Platform Cache register CPCHDBCR0 bit
21 to 1'b1. This may have a small impact on synthetic write bandwidth
benchmarks but should have a negligible impact on real code."Signed-off-by: Scott Wood
Signed-off-by: Andy Fleming
03 May, 2013
1 commit
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On P204x/P304x/P50x0 Rev1.0, USB transmit will result in false internal
multi-bit ECC errors, which has impact on performance, so software should
disable all ECC reporting from USB1 and USB2.In formal release document, the errata number should be USB14 instead of USB138.
Signed-off-by: xulei
Signed-off-by: Roy Zang
Signed-off-by: Kumar Gala
Signed-off-by: xulei
Signed-off-by: Andy Fleming
31 Jan, 2013
1 commit
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When CoreNet Fabric (CCF) internal resources are consumed by the cores,
inbound SRIO messaging traffic through RMan can put the device into a
deadlock condition.This errata workaround forces internal resources to be reserved for
upstream transactions. This ensures resources exist on the device for
upstream transactions and removes the deadlock condition.The Workaround is for the T4240 silicon rev 1.0.
Signed-off-by: Shengzhou Liu
Signed-off-by: Andy Fleming
28 Nov, 2012
3 commits
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Due to SerDes configuration error, if we set the PCI-e controller link width
as x8 in RCW and add a narrower width(such as x4, x2 or x1) PCI-e device to
PCI-e slot, it fails to train down to the PCI-e device's link width. According
to p4080ds errata PCIe-A003, we reset the PCI-e controller link width to x4 in
u-boot. Then it can train down to x2 or x1 width to make the PCI-e link between
RC and EP.Signed-off-by: Yuanquan Chen
Signed-off-by: Andy Fleming -
The work-around for erratum A-004580 ("Internal tracking loop can falsely
lock causing unrecoverable bit errors") is implemented via the PBI
(pre-boot initialization code, typically attached to the RCW binary).
This is because the work-around is easier to implement in PBI than in
U-Boot itself.It is still useful, however, for the 'errata' command to tell us whether
the work-around has been applied. For A-004580, we can do this by verifying
that the values in the specific registers that the work-around says to
update.This change requires access to the SerDes lane sub-structure in
serdes_corenet_t, so we make it a named struct.Signed-off-by: Timur Tabi
Signed-off-by: Andy Fleming -
The work-around for erratum A-004849 ("CoreNet fabric (CCF) can exhibit a
deadlock under certain traffic patterns causing the system to hang") is
implemented via the PBI (pre-boot initialization code, typically attached
to the RCW binary). This is because the work-around is easier to implement
in PBI than in U-Boot itself.It is still useful, however, for the 'errata' command to tell us whether
the work-around has been applied. For A-004849, we can do this by verifying
that the values in the specific registers that the work-around says to
update.Signed-off-by: Timur Tabi
Signed-off-by: Andy Fleming
23 Oct, 2012
3 commits
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After DDR controller is enabled, it performs a calibration for the
transmit data vs DQS paths. During this calibration, the DDR controller
may make an inaccurate calculation, resulting in a non-optimal tap point.Signed-off-by: York Sun
Signed-off-by: Andy Fleming -
Boot space translation utilizes the pre-translation address to select
the DDR controller target. However, the post-translation address will be
presented to the selected DDR controller. It is possible that the pre-
translation address selects one DDR controller but the post-translation
address exists in a different DDR controller when using certain DDR
controller interleaving modes. The device may fail to boot under these
circumstances. Note that a DDR MSE error will not be detected since DDR
controller bounds registers are programmed to be the same when configured
for DDR controller interleaving.Signed-off-by: York Sun
Signed-off-by: Andy Fleming -
Erratum: A-004034
Affects: SRIODescription: During port initialization, the SRIO port performs
lane synchronization (detecting valid symbols on a lane) and
lane alignment (coordinating multiple lanes to receive valid data
across lanes). Internal errors in lane synchronization and lane
alignment may cause failure to achieve link initialization at
the configured port width.An SRIO port configured as a 4x port may see one of these scenarios:
1. One or more lanes fails to achieve lane synchronization.
Depending on which lanes fail, this may result in downtraining
from 4x to 1x on lane 0, 4x to 1x on lane R (redundant lane).2. The link may fail to achieve lane alignment as a 4x, even
though all 4 lanes achieve lane synchronization, and downtrain
to a 1x. An SRIO port configured as a 1x port may fail to complete
port initialization (PnESCSR[PU] never deasserts) because of
scenario 1.Impact: SRIO port may downtrain to 1x, or may fail to complete
link initialization. Once a port completes link initialization
successfully, it will operate normally.Signed-off-by: Liu Gang
Signed-off-by: Andy Fleming
22 Oct, 2012
1 commit
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P4080 Rev3.0 fixes ESDHC13 errata, so update the code to make the
workaround conditional.
In formal release document, the errata number should be ESDHC13 instead
of ESDHC136.Signed-off-by: Roy Zang
Signed-off-by: Andy Fleming
24 Aug, 2012
1 commit
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Erratum A004510 says that under certain load conditions, modified
cache lines can be discarded, causing data corruption.To work around this, several CCSR and DCSR register updates need to be
made in a careful manner, so that there is no other transaction in
corenet when the update is made.The update is made from a locked cacheline, with a delay before to flush
any previous activity, and a delay after to flush the CCSR/DCSR update.
We can't use a readback because that would be another corenet
transaction, which is not allowed.We lock the subsequent cacheline to prevent it from being fetched while
we're executing the previous cacheline. It is filled with nops so that a
branch doesn't cause us to fetch another cacheline.Ordinarily we are running in a cache-inhibited mapping at this point, so
we temporarily change that. We make it guarded so that we should never
see a speculative load, and we never do an explicit load. Thus, only the
I-cache should ever fill from this mapping, and we flush/unlock it
afterward. Thus we should avoid problems from any potential cache
aliasing between inhibited and non-inhibited mappings.NOTE that if PAMU is used with this patch, it will need to use a
dedicated LAW as described in the erratum. This is the responsibility
of the OS that sets up PAMU.Signed-off-by: Scott Wood
Signed-off-by: Andy Fleming
23 Aug, 2012
1 commit
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This erratum applies to the following SoCs:
P4080 rev 1.0, 2.0, fixed in rev 3.0
P2041 rev 1.0, 1.1, fixed in rev 2.0
P3041 rev 1.0, 1.1, fixed in rev 2.0.Workaround for erratum NMG_CPU_A011 is enabled by default. This workaround
may degrade performance. P4080 erratum CPU22 shares the same workaround.
So it is always enabled for P4080. For other SoCs, it can be disabled by
hwconfig with syntax:fsl_cpu_a011:disable
Signed-off-by: York Sun
Signed-off-by: Andy Fleming
07 Jul, 2012
3 commits
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Erratum NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in rev 3.0.
It also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1. It shares the
same workaround as erratum CPU22. Rearrange registers usage in assembly
code to avoid accidental overwriting.Signed-off-by: York Sun
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We don't care E bit of SVR in most cases. Clear E bit for SVR_SOC_VER().
This will simplify the coding. Use IS_E_PROCESSOR() to identify SoC with
encryption. Remove all _E entries from SVR list and CPU list.Signed-off-by: York Sun
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Workaround for erratum CPU22 applies to P4080 rev 1 and rev 2 only.
Signed-off-by: York Sun
29 Nov, 2011
2 commits
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Erratum A-003474: Internal DDR calibration circuit is not supported
Impact:
Experience shows no significant benefit to device operation with
auto-calibration enabled versus it disabled. To ensure consistent timing
results, Freescale recommends this feature be disabled in future customer
products. There should be no impact to parts that are already operating
in the field.Workaround:
Prior to setting DDR_SDRAM_CFG[MEM_EN]=1, do the following:
1. Write a value of 0x0000_0015 to the register at offset
CCSRBAR + DDR OFFSET + 0xf30
2. Write a value of 0x2400_0000 to the register at offset
CCSRBAR + DDR OFFSET + 0xf54Signed-off-by: York Sun
Signed-off-by: Kumar Gala -
Erratum A-003999: Running Floating Point instructions requires special
initialization.Impact:
Floating point arithmetic operations may result in an incorrect value.Workaround:
Perform a read modify write to set bit 7 to a 1 in SPR 977 before
executing any floating point arithmetic operation. This bit can be set
when setting MSR[FP], and can be cleared when clearing MSR[FP].
Alternatively, the bit can be set once at boot time, and never cleared.
There will be no performance degradation due to setting this bit.Signed-off-by: Kumar Gala
08 Nov, 2011
1 commit
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Erratum NMG_eTSEC129 (eTSEC86 in MPC8548 document) applies to some early
verion silicons. This workaround detects if the eTSEC Rx logic is properly
initialized, and reinitialize the eTSEC Rx logic.Signed-off-by: Gong Chen
Signed-off-by: Zhao Chenhui
Signed-off-by: Kumar Gala
03 Oct, 2011
2 commits
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The erratum NMG_LBC103 is LBIU3 in MPC8548 errata document.
Any local bus transaction may fail during LBIU resynchronization
process when the clock divider [CLKDIV] is changing. Ensure there
is no transaction on the local bus for at least 100 microseconds
after changing clock divider LCRR[CLKDIV].Refer to the erratum LBIU3 of mpc8548.
Signed-off-by: Zhao Chenhui
Signed-off-by: Kumar Gala -
Erratum NMG_DDR120 (DDR19 in MPC8548 errata document) applies to some
early version silicons. The default settings of the DDR IO receiver
biasing may not work at cold temperature. When a failure occurs,
a DDR input latches an incorrect value. The workaround will set the
receiver to an acceptable bias point.Signed-off-by: Gong Chen
Signed-off-by: Zhao Chenhui
Signed-off-by: Kumar Gala
30 Sep, 2011
3 commits
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Issue: Address masking doesn't work properly.
When sum of the base address, defined by BA, and memory bank size,
defined by AM, exceeds 4GB (0xffff_ffff) then AMASKn[AM] doesn't mask
CSPRn[BA] bits.Impact:
This will impact booting when we are reprogramming CSPR0(BA) and
AMASK0(AMASK) while executing from NOR Flash.Workaround:
Re-programming of CSPR(BA) and AMASK is done while not executing from NOR
Flash. The code which programs the BA and AMASK is executed from L2-SRAM.Signed-off-by: Poonam Aggrwal
Signed-off-by: Kumar Gala -
Issue:
Peripheral connected to IFC_CS3 may hamper booting from IFC.Impact:
Boot from IFC may not be successful if IFC_CS3 is used.Workaround:
If IFC_CS3 is used, gate IFC_CS3 while booting from NAND or NOR.
Also Software should select IFC_CS3 using PMUXCR[26:27] = 0x01.Signed-off-by: Poonam Aggrwal
Signed-off-by: Kumar Gala -
Issue:
The NOR-FCM does not support access to unaligned addresses for 16 bit port sizeImpact:
When 16 bit port size is used, accesses not aligned to 16 bit address boundary
will result in incorrect dataWorkaround:
The workaround is to switch to GPCM mode for NOR Flash access.Signed-off-by: Poonam Aggrwal
Signed-off-by: Kumar Gala
29 Apr, 2011
1 commit
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SerDes PLL bandwidth default setting is incorrect when no lanes are
configured as PCI Express.Signed-off-by: Timur Tabi
Signed-off-by: Kumar Gala
28 Apr, 2011
1 commit
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Signed-off-by: Emil Medve
Signed-off-by: Timur Tabi
Signed-off-by: Kumar Gala
03 Feb, 2011
3 commits
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Workaround for the following errata:
DDR111 - MCKE signal may not function correctly at assertion of HRESET
DDR134 - The automatic CAS-to-Preamble feature of the DDR controller can
calibrate to incorrect valuesThese two workarounds must be implemented together because they touch
common registers.Signed-off-by: York Sun
Signed-off-by: Kumar Gala -
Use unique erratum number instead of platform number.
Enable command that reports errata on MPC8572DS.Signed-off-by: York Sun
Signed-off-by: Kumar Gala -
Data timeout counter (SYSCTL[DTOCV]) is not reliable for values of 4, 8,
and 12. Program one more than the desired value: 4 -> 5, 8 -> 9, 12 -> 13.Signed-off-by: Kumar Gala
20 Jan, 2011
1 commit
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Erratum DDR-A003 requires workaround to correctly set RCW10 for registered DIMM.
Also adding polling after enabling DDR controller to ensure completion.Signed-off-by: York Sun
Signed-off-by: Kumar Gala
14 Jan, 2011
1 commit
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Simultaneous FCM and GPCM or UPM operation may erroneously trigger bus
monitor timeout. Set timeout to maximum to avoid.Based on a patch from Lan Chunhe
Signed-off-by: Kumar Gala