14 Apr, 2019
6 commits
-
Place ipuv3 files and headers in custom driver subdirectory.
Signed-off-by: Anatolij Gustschin
-
Extend the driver to build with DM_VIDEO enabled. DTS files
must additionally include 'u-boot,dm-pre-reloc' property in
soc and ipu nodes to enable driver binding to ipu device.Signed-off-by: Anatolij Gustschin
-
Disable this support for cm_fx6 to avoid breakage.
Signed-off-by: Soeren Moch
-
Do not report negative sector numbers for disks > 1TB, do not limit
sector numbers to 32 bit if CONFIG_SYS_64BIT_LBA is enabled.Signed-off-by: Soeren Moch
-
Signed-off-by: Lukasz Majewski
Reviewed-by: Stefan Agner -
The NXP's FEC driver can be reused on vf610 device (with DM).
Signed-off-by: Lukasz Majewski
Reviewed-by: Stefan Agner
13 Apr, 2019
3 commits
-
stm32 patches for v2019.07-rc1
- Add trusted boot with TF-A for stm32mp1
- stm32mp1 dts files sync'ed with Linux version
- add STM32MP1 Discovery boards (DK1 and DK2)
- add STMFX gpio expander driver
- misc improvement for stm3mp1 supports
- rename stpmu1 to stpmic1 (official name)
- stm32_qspi: move to exec_op (spi nor driver for stm32 mpu and mcu)
- add STM32 FMC2 NAND flash controller driver -
- Misc dts files sync'ed with Linux version (Chris)
- Orion watchdog fix (Chris)
- kwbimage changed to also support Marvell bin_hdr binary (Chris)
- Add DM support to enable CONFIG_BLK for sata_mv (Stefan)
- Enable BLK on multiple platforms (Stefan)
- Misc minor fixes to AXP theadorable board (Stefan)
- Correct logic for DM_SCSI + unconverted drivers check (stefan)
- Misc changes to kirkwood to enable DM_USB here (Chris)
- Change ahci_mvebu to enable usage on A38x (Baruch)
- Update the kirkwood entry in git-mailrc (Baruch)
- Misc minor improvements (turris, documentation) (Baruch)
- Enhance sata_mv to support Kirkwood as well (Michael)
- Add wdt command (Michael)
- Add Marvell integrated CPUs (MSYS) support with DB-XC3-24G4XG
board support (Chris)
12 Apr, 2019
31 commits
-
The driver adds the support for the STMicroelectronics FMC2 NAND
Controller found on STM32MP SOCs.This patch adds the polling mode, a basic mode that do not need
any DMA channels.Only NAND_ECC_HW mode is actually supported.
The driver supports a maximum 8k page size.
The following ECC strength and step size are currently supported:
- nand-ecc-strength = , nand-ecc-step-size = (BCH8)
- nand-ecc-strength = , nand-ecc-step-size = (BCH4)
- nand-ecc-strength = , nand-ecc-step-size = (Extended ECC
based on Hamming)This patch has been tested on Micron MT29F8G08ABACAH4.
Signed-off-by: Christophe Kerello
-
We are facing issues in the driver since SPI NOR framework has moved
on SPI MEM framework, and SPI NAND framework is not running properly
with the current driver.To be able to solve issues met on SPI NOR Flashes and to be able to
support SPI NAND Flashes, the driver has been reworked. We are now using
exec_op ops instead of using xfer ops.Thanks to this rework, the driver has been successfully tested with:
- mx66l51235l SPI NOR Flash on stm32f746 SOC
- n25q128a SPI NOR Flash on stm32f769 SOC
- mx66l51235l SPI NOR Flash on stm32mp1 SOC
- mt29f2g01abagd SPI NAND Flash on stm32mp1 SOCSigned-off-by: Christophe Kerello
Tested-by: Patrick DELAUNAY
Reviewed-by: Patrick DELAUNAY -
This patch adds pinctrl/GPIO driver for STMicroelectronics
Multi-Function eXpander (STMFX) GPIO expander.
STMFX is an I2C slave controller, offering up to 24 GPIOs.
The driver relies on UCLASS_PINCTRL and UCLASS_GPIO.Signed-off-by: Patrick Delaunay
Signed-off-by: Patrice Chotard -
Add functions to read/update the non volatile memory of STPMIC1
(8 bytes-register at 0xF8 address) and allow access
with fuse command (bank=1, word > 0xF8).For example:
STM32MP> fuse read 1 0xf8 8
Reading bank 1:Word 0x000000f8: 000000ee 00000092 000000c0 00000002
Word 0x000000fc: 000000f2 00000080 00000002 00000033Signed-off-by: Patrick Delaunay
-
Add sysreset support, and support power switch off request,
needed by poweroff command.Signed-off-by: Patrick Delaunay
-
Alignment with STPMIC1 datasheet
s/MAIN_CONTROL_REG/MAIN_CR/g
s/MASK_RESET_BUCK/BUCKS_MRST_CR/g
s/MASK_RESET_LDOS/LDOS_MRST_CR/g
s/BUCKX_CTRL_REG/BUCKX_MAIN_CR/g
s/VREF_CTRL_REG/REFDDR_MAIN_CR/g
s/LDOX_CTRL_REG/LDOX_MAIN_CR/g
s/USB_CTRL_REG/BST_SW_CR/g
s/STPMIC1_NVM_USER_STATUS_REG/STPMIC1_NVM_SR/g
s/STPMIC1_NVM_USER_CONTROL_REG/STPMIC1_NVM_CR/g
and update all the associated defines.Signed-off-by: Patrick Delaunay
-
Alignment with kernel driver name & binding
introduced by https://patchwork.kernel.org/cover/10761943/
to use the final marketing name = STPMIC1.Signed-off-by: Patrick Delaunay
Reviewed-by: Lukasz Majewski -
Prepare file modification for kernel alignment and
rename driver to stpmic1.Signed-off-by: Patrick Delaunay
Reviewed-by: Lukasz Majewski -
SW impact for Rev 1.2 of STPMIC1 in U-Boot:
Buck converters output voltage change for Buck1
=> Vdd min 0,725 to max 1,5V instead of 0.6V to 1.35V
(see STPMIC1 datasheet / chapter 5.3 Buck converters)Signed-off-by: Patrick Delaunay
-
Add support of trusted boot, using TF-A as first stage bootloader,
The boot sequence is
BootRom >=> TF-A.stm32 (clock & DDR) >=> U-Boot.stm32The TF-A monitor provides secure monitor with support of SMC
- proprietary to manage secure devices (BSEC for example)
- PSCI for powerThe same device tree is used for STMicroelectronics boards with
basic boot and with trusted boot.Signed-off-by: Patrick Delaunay
-
Pbias voltage should match the IO voltage set for the SD card. With the
latest pbias change to 3.3V, update the capabilities and IO voltages
settings to 3.3V.Signed-off-by: Faiz Abbas
-
As per recent TRM[1], PBIAS cell on dra7 devices supports
3.3v and not 3.0v as documented earlier.Update PBIAS regulator max voltage and the voltage written
in the driver to reflect this.[1] http://www.ti.com/lit/pdf/sprui30
Signed-off-by: Faiz Abbas
-
The SPL image overflows when cpsw dt nodes are added and SPL_OF_CONTROL
is enabled. Use static platdata instead to save space.Signed-off-by: Faiz Abbas
-
Add DM_FLAG_PRE_RELOC to make the driver probe in SPL.
Signed-off-by: Faiz Abbas
-
The ofdata_to_platdata function should not be called if OF_CONTROL is
not enabled because fdtdec_* calls will fail. Block the function with
OF_CONTROLSigned-off-by: Faiz Abbas
-
ti_cm_get_macid() is used to get a syscon node from the dt, read the
efuse address and then assign the macid read from the address. Divide
these two steps into separate functions one of which can be called from
ofdata_to_platdata() while the other can be called from _probe(). This
ensures that platdata can be assigned statically in a board file when
OF_CONTROL is not enabled. Also add a macid_sel_compat in private data
to get information about the macid byte placement.Signed-off-by: Faiz Abbas
-
Convert cpsw_platform_data to a pointer in cpsw_priv. Allocate it
dynamically and assign it as a part of eth_pdata. This helps in
isolating platform data handling and implementing platdata for SPL
in a board file.Signed-off-by: Faiz Abbas
-
cpsw_phy_sel() is a configuration step that should not be in
ofdata_to_platdata(). Add phy_sel_compat to the cpsw_platform_data
structure so that it is accessible in _probe. Then move the call of
cpsw_phy_sel() to _probe.Signed-off-by: Faiz Abbas
-
DMSC can use certain amount of msmc memory available in the
system. Also certain part of msmc memory can be marked as L3
cache using board config. But users might not know what size
is being used and the remaining available msmc memory. In order
to fix this TISCI protocol provides a messages that can query
the available msmc memory in the system. Add support for this
message.Signed-off-by: Lokesh Vutla
-
Enhance the netcp driver to support phys that can be configured
for internal delay (rgmii-id, rgmii-rxid, rgmii-txid)Signed-off-by: Murali Karicheri
Acked-by: Joe Hershberger -
Marvell's switch chips with integrated CPUs (collectively referred to as
MSYS) share common ancestry with the Armada SoCs. Some of the IP blocks
(e.g. xor) are located at different addresses and DFX server exists as a
separate target on the MBUS (on Armada-38x it's just part of the core
complex registers).Signed-off-by: Chris Packham
Reviewed-by: Stefan Roese
Signed-off-by: Stefan Roese -
The kirkwood devices are compatible with this driver.
Signed-off-by: Michael Walle
Reviewed-by: Chris Packham
Reviewed-by: Stefan Roese
Signed-off-by: Stefan Roese -
Fix the worng include and offset macros.
Signed-off-by: Michael Walle
Reviewed-by: Stefan Roese
Signed-off-by: Stefan Roese -
This fixes a compile error on kirkwood.
Signed-off-by: Michael Walle
Reviewed-by: Chris Packham
Reviewed-by: Stefan Roese
Signed-off-by: Stefan Roese -
With board_ahci_enable() implementation for Armada 38x in place we can
now enable 38x support in the ahci_mvebu driver.Signed-off-by: Baruch Siach
Reviewed-by: Stefan Roese
Signed-off-by: Stefan Roese -
This patch adds DM support to the Armada XP SATA driver. This is needed
to enable CONFIG_BLK on this platform. It adds the SATA controller as
AHCI device, which is strictly speaking not correct, as the controller
is not AHCI compatible. But the U-Boot AHCI uclass interface enables
the usage of this DM driver and the creation of the corresponding BLK
devices.This conversion is done to get rid of the compile warning:
Reviewed-by: Chris Packham===================== WARNING ======================
This board does not use CONFIG_DM_SCSI. Please update
the storage controller to use CONFIG_DM_SCSI before the v2019.07 release.
Failure to update by the deadline may result in board removal.
See doc/driver-model/MIGRATION.txt for more info.
====================================================Signed-off-by: Stefan Roese
Cc: Simon Glass
Cc: Tom Rini -
The generic wdt_start API expects to be called with the timeout in
milliseconds. Update the orion_wdt driver to accept a timeout in
milliseconds and use the clock rate specified in the dts to convert the
timeout to an appropriate value for the timer reload register.Signed-off-by: Chris Packham
Reviewed-by: Stefan Roese
Signed-off-by: Stefan Roese -
When run from the SPL the mvebu targets are using the hardware default
offset for the SoC peripherals. devfdt_get_addr_size_index() understands
how to deal with this via dm_get_translation_offset() so use this
instead of fdtdec_get_addr_size_auto_noparent().Signed-off-by: Chris Packham
Reviewed-by: Stefan Roese
Signed-off-by: Stefan Roese -
Merge drivers/soc/keystone/ into drivers/soc/ti/
and convert CONFIG_TI_KEYSTONE_SERDES into Kconfig.Signed-off-by: Vignesh R
Reviewed-by: Tom Rini -
The UDMA-P is intended to perform similar (but significantly upgraded) functions
as the packet-oriented DMA used on previous SoC devices. The UDMA-P module
supports the transmission and reception of various packet types.
The UDMA-P also supports acting as both a UTC and UDMA-C for its internal
channels. Channels in the UDMA-P can be configured to be either Packet-Based or
Third-Party channels on a channel by channel basis.The initial driver supports:
- MEM_TO_MEM (TR mode)
- DEV_TO_MEM (Packet mode)
- MEM_TO_DEV (Packet mode)Signed-off-by: Peter Ujfalusi
Signed-off-by: Grygorii Strashko
Signed-off-by: Vignesh R -
The Ring Accelerator (RINGACC or RA) provides hardware acceleration to
enable straightforward passing of work between a producer and a consumer.
There is one RINGACC module per NAVSS on TI AM65x SoCs.The RINGACC converts constant-address read and write accesses to equivalent
read or write accesses to a circular data structure in memory. The RINGACC
eliminates the need for each DMA controller which needs to access ring
elements from having to know the current state of the ring (base address,
current offset). The DMA controller performs a read or write access to a
specific address range (which maps to the source interface on the RINGACC)
and the RINGACC replaces the address for the transaction with a new address
which corresponds to the head or tail element of the ring (head for reads,
tail for writes). Since the RINGACC maintains the state, multiple DMA
controllers or channels are allowed to coherently share the same rings as
applicable. The RINGACC is able to place data which is destined towards
software into cached memory directly.Supported ring modes:
- Ring Mode
- Messaging Mode
- Credentials Mode
- Queue Manager ModeTI-SCI integration:
Texas Instrument's System Control Interface (TI-SCI) Message Protocol now
has control over Ringacc module resources management (RM) and Rings
configuration.The Ringacc driver manages Rings allocation by itself now and requests
TI-SCI firmware to allocate and configure specific Rings only. It's done
this way because, Linux driver implements two stage Rings allocation and
configuration (allocate ring and configure ring) while TI-SCI Message
Protocol supports only one combined operation (allocate+configure).Signed-off-by: Grygorii Strashko
Signed-off-by: Vignesh R
