06 Oct, 2016
5 commits
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PCM052 SoMs may be equipped with various sizes of DDR.
Keep default of 256MB; new PCM052-based targets will
specify their actual DDR size.Linux command line is auto-adjusted to DDR size.
Signed-off-by: Albert ARIBAUD (3ADEV)
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This format can be flashed directly at address 0 of
the NAND FLASH, as it contains all necessary headers.Signed-off-by: Albert ARIBAUD (3ADEV)
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Add the 'm4go' command to pcm052-based targets.
It loads scatter file images.Signed-off-by: Albert ARIBAUD (3ADEV)
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Signed-off-by: Albert ARIBAUD (3ADEV)
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Merge 'spare' into 'bootloader' partition
Use same partition for ramdisk and rootfs boot scenarios.
Remove 'ramdisk' partition, use 'rootfs' for ramdisk
(ramdisk and nand boot scenarios are mutually exclusive).
Expand last partition to end of actual NAND size.
Adjust UBIFS rootfs boot kernel arguments.Signed-off-by: Albert ARIBAUD (3ADEV)
05 Oct, 2016
3 commits
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>From TO1.1, SNVS adds internal pull up control for POR_B,
the register filed is GPBIT[1:0], after system boot up,
it can be set to 2b'01 to disable internal pull up.
It can save about 30uA power in SNVS mode.Signed-off-by: Peng Fan
Cc: Stefano Babic -
For i.MX6, the mux width is 4, not 3. So enlarge the width.
IOMUX_CONFIG_LPSR is changed from 0x8 to 0x20 to not use bit 3 of mux.Signed-off-by: Peng Fan
Cc: Stefano Babic -
Currently the bmode "usb" uses BOOT_CFG1 to 0x01, -which means
BOOT_CFG1[7:4] is set to b0000. According to Table 8-7 Boot
Device Selection this is NOR/OneNAND and not Reserved.Use 0x10 which leads to b0001, which is a Reserved boot device.
With that the SoC reliably falls back to the serial loader.Cc: Troy Kisky
Signed-off-by: Stefan Agner
Tested-by: Troy Kisky
04 Oct, 2016
29 commits
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Add i.MX6ULL EVK board support:
Add device tree file, which is copied from NXP Linux.
Enabled DM_MMC, DM_GPIO, DM_I2C, DM_SPI, PINCTRL, DM_REGULATOR.
The uart iomux settings are still keeped in board file.Boot Log:
U-Boot 2016.09-rc1-00366-gbb419ef-dirty (Aug 11 2016 - 13:08:58 +0800)CPU: Freescale i.MX6ULL rev1.0 at 396MHz
CPU: Commercial temperature grade (0C to 95C) at 15C
Reset cause: POR
Model: Freescale i.MX6 ULL 14x14 EVK Board
Board: MX6ULL 14x14 EVK
DRAM: 512 MiB
MMC: initialized IMX pinctrl driver
FSL_SDHC: 0, FSL_SDHC: 1
In: serial
Out: serial
Err: serial
Net: CPU Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot: 0
=> mmc dev 1
switch to partitions #0, OK
mmc1 is current deviceSigned-off-by: Peng Fan
Cc: Stefano Babic -
Need to initialize mmc->dev when probe, or will met
"dev_get_uclass_priv: null device", when `mmc dev 1`.Signed-off-by: Peng Fan
Cc: Stefano Babic
Cc: Simon Glass
Cc: Jaehoon Chung
Reviewed-by: Simon Glass -
Add device tree for i.MX6ULL.
Signed-off-by: Peng Fan
Cc: Simon Glass
Cc: Stefano Babic -
Add i.mx6ul clock header, copied from kernel commit (29b4817d401).
i.MX6ULL reuse the file in Linux Kernel, so let's keep the same.Signed-off-by: Peng Fan
Cc: Simon Glass
Cc: Stefano Babic -
Add pinctrl defines for NXP i.MX 6ULL.
Since i.MX6ULL reuses some definitions of i.MX6UL,
also add i.MX6UL pinctrl defines from linux kernel commit (29b4817d401).Signed-off-by: Peng Fan
Cc: Simon Glass
Cc: Stefano Babic -
There two iomuxc for i.MX6ULL. one iomuxc is compatible is i.MX6UL,
the other iomuxc is for SVNS usage, similar with the one in mx7.Signed-off-by: Peng Fan
Cc: Stefano Babic
Cc: Simon Glass -
SNVS TAMPER pin and BOOT MODE pins are in SNVS IOMUXC module,
not in IOMUXC, so correct the related registers' offset.Use IOMUX_CONFIG_LPSR flag for these pins, so we can differentiate
them from iomuxc pins.Signed-off-by: Peng Fan
Cc: Stefano Babic
Cc: "Benoît Thébaudeau" -
Per to design team, on i.MX6UL, the LDO 1.2V bandgap voltage
is 30mV higher, so we need to adjust the REFTOP_VBGADJ(anatop
MISC0 bit[6:4]) setting to 2b'110.Signed-off-by: Peng Fan
Signed-off-by: Bai Ping
Cc: Stefano Babic -
Since the mx6ull adds the AIPS3, so enable its initialization.
Signed-off-by: Peng Fan
Signed-off-by: Ye Li
Cc: Stefano Babic -
Update memory map address for mx6ull.
Signed-off-by: Peng Fan
Signed-off-by: Ye Li
Cc: Stefano Babic -
Update Clock settings and CCM register map for i.MX6ULL.
Signed-off-by: Peng Fan
Signed-off-by: Ye Li
Cc: Stefano Babic -
Adjust POR_B settings on i.MX6ULL according to IC design
team's suggestion:2'b00 : always PUP100K
2'b01 : PUP100K when PMIC_ON_REQ || SOC_NOT_FAIL
2'b10 : always disable PUP100K
2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL -- recommended settingSigned-off-by: Peng Fan
Signed-off-by: Anson Huang
Cc: Stefano Babic -
Update misc SOC related settings for i.MX6ULL, such as FEC mac address,
cpu speed grading and mmdc channel mask clearing.Also update s_init to skip pfd reset.
Signed-off-by: Peng Fan
Cc: Stefano Babic -
Since MX6ULL select MX6UL, we can not use IS_ENABLED(CONFIG_MX6UL) here,
because this piece code is only for i.MX6UL.Signed-off-by: Peng Fan
Cc: Stefano Babic
Reviewed-by: Stefano Babic -
Rom already initialized clock at 396M and 132M for arm core and ahb,
so skip setting them again in U-Boot.Signed-off-by: Peng Fan
Cc: Stefano Babic
Reviewed-by: Stefano Babic -
The i.MX6ULL's GPT supportting taking OSC as clock source.
Add i.MX6ULL support.Signed-off-by: Peng Fan
Signed-off-by: Ye Li
Cc: Stefano Babic
Reviewed-by: Stefano Babic -
i.MX6ULL has two 128 bits fuse banks, bank 7 and bank 8,
while other banks use 256 bits. So we have to adjust the
word and bank index when accessing the bank 8.When in command line `fuse read 8 0 1`, you can image
`fuse read 7 4 1` in the ocotp driver implementation for 6ULL.When programming, we use word index, so need to fix bank7/8 programming
for i.mx6ull.For example: fuse prog 8 3 1; The word index is (8 << 3 | 3) --> 67.
But actully it should be (7 << 3 | 7) ---> 63.
So fix it.Signed-off-by: Peng Fan
Cc: Stefano Babic -
Introduce is_mx6ull macro.
Signed-off-by: Peng Fan
Cc: Stefano Babic -
i.MX6ULL is derivative from i.MX6UL, so select MX6UL for MX6ULL.
If need to differenate MX6ULL from MX6UL, use CONFIG_MX6ULLSigned-off-by: Peng Fan
Signed-off-by: Ye Li
Cc: Stefano Babic -
Add i.MX6ULL major cpu type.
Signed-off-by: Peng Fan
Signed-off-by: Ye Li
Cc: Stefano Babic
Reviewed-by: Stefano Babic -
Add iomux header file for i.MX6ULL.
Signed-off-by: Peng Fan
Signed-off-by: Ye Li
Cc: Stefano Babic
Reviewed-by: Stefano Babic -
Correct name is "Boundary Devices".
Signed-off-by: Fabio Estevam
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There is no stable mmcblk device numbering over different linux versions.
Enable CMD_PART to be able to query the UUID of the root filesystem partition.
So we can pass root=PARTUUID=XXX instead of root=/dev/mmcblkXpY in bootargs.
Leave the default environment as is for now to stay compatible with original
TBS settings.Signed-off-by: Soeren Moch
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Currently the driver asserts WDOG_B by clearing WCR_WDA bit when
enabling the watchdog. Do not clear WCR_WDA.Signed-off-by: Ross Parker
Cc: Stefano Babic -
The CPU detection macro is_mx6dq returns 0 on an i.MX6DQP, so we need to
check for it explicitly in order to correctly initialize the pads when
CONFIG_MX6QDL is defined.Signed-off-by: Filip Brozovic
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The linux kernel imx_v6_v7_defconfig sets the user/kernel memory split
to 3G/1G now (was 2G/2G before). We have to adapt the BOOTMAPSZ so that
the decompressor finds zImage and dtb in lowmem.Signed-off-by: Soeren Moch
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When using SPL on i.mx6 we frequently notice some DDR initialization
mismatches between the SPL code and the non-SPL code.This causes stability issues like the ones reported at 7dbda25ecd6d7c
("mx6ul_14x14_evk: Pass refsel and refr fields to avoid hang") and also:
http://lists.denx.de/pipermail/u-boot/2016-September/266355.html .As the non-SPL code have been tested for long time and proves to be reliable,
let's configure the DDR in the exact same way as the non-SPL case.The idea is simple: just use the DCD table and write directly to the DDR
registers.Retrieved the DCD tables from:
board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg
and
board/freescale/mx6sabresd/mx6qp.cfg
(NXP U-Boot branch imx_v2015.04_4.1.15_1.0.0_ga)This method makes it easier for people converting from non-SPL to SPL code.
Other benefit is that the SPL binary size is reduced from 44 kB to 39.9 kB.
Signed-off-by: Fabio Estevam
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The videoargs script is kernel version dependent and since wandboard
uses distro config, there is no need to handle videoargs locally.In case such video related settings are needed, then the proper
location would be the distro extlinux.conf or boot.scr files.So remove 'videoargs' script.
Signed-off-by: Fabio Estevam
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A kernel hang is observed when running wandboard 3.14 kernel and
going to the lowest operational point of cpufreq:# ifconfig eth0 down
# echo 1 > /sys/class/graphics/fb0/blankThe problem is caused by incorrect setting of the REFR field
of register MDREF. Setting it to 4 refresh commands per refresh
cycle fixes the hang.Signed-off-by: Fabio Estevam
03 Oct, 2016
2 commits
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Signed-off-by: Tom Rini
02 Oct, 2016
1 commit
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Authentication of images in Falcon Mode is not supported. Do not enable
SPL_OS_BOOT when TI_SECURE_DEVICE is enabled. This prevents attempting
to directly load kernel images which will fail, for security reasons,
on HS devices, the board is locked if a non-authenticatable image load
is attempted, so we disable attempting Falcon Mode.Signed-off-by: Andrew F. Davis
Reviewed-by: Tom Rini
Acked-by: Lokesh Vutla
