03 Nov, 2018
15 commits
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iMX8MM DDR3L validation board uses FPGA to link with SPI NOR flash
on ECSPI1 port. Update the codes and configurations to enable the
ECSPI1 to access SPI NOR in u-boot.Signed-off-by: Ye Li
Reviewed-by: Peng Fan -
iMX8MM DDR3L validation board uses GD25LQ16, but its id is not in
u-boot flash ids table. Add the new id and parameters into the table.Signed-off-by: Ye Li
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Generate the key blob and store it to the last block of boot1 partition
after setting the rpmb key. The key blob should be checked in spl and be
passed to Trusty OS if it's valid. If the key blob are damaged, RPMB
storage proxy service will return fail and should make the device hang.Test: Build and boot ok on imx8qm/qxp.
Change-Id: Ia274cd72109ab6ae15920e91b2a2008e1f1e667c
Signed-off-by: Ji Luo -
Add new hwcrypto tipc command and handler to generate blob with
CAAM.Test: Message exchange with trusty and blob encapsulate/decapsulate ok.
Change-Id: I925b47cb3e22eeddf4c89e84a9c994d2f30423fe
Signed-off-by: Ji Luo -
Use CAAM to accelerate SHA256 hash calculation in AVB,
this will reduce u-boot boot time, about 570ms can be
saved for imx8qxp.Test: Build and boot ok for imx8qxp.
Change-Id: Idbbd781e5ad8e7d6cd8865190d7547c165d02190
Signed-off-by: Ji Luo -
Add new service 'hwcrypto' to handle CAAM related work
with Trusty OS. Add tipc interface to accelerate hash
calculation with CAAM.Test: Service connect and message exchange with Trusty OS
are ok.Change-Id: Ia870c3ad2ff30af987f327a9777a8b32f53593db
Signed-off-by: Ji Luo -
Add defconfig for nand on lpddr4 arm2 board
Signed-off-by: Teo Hall
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Add include files necessary for supporting SPL on QXP
ARM2 boardSigned-off-by: Teo Hall
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Add implementation necessary for supporting SPL on QXP
ARM2 board with dynamic offset detection from container header.Signed-off-by: Teo Hall
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The first DRAM BANK size should be 2GB and the load addr
are 0x80080000.Signed-off-by: Peng Fan
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If the resource is not owned by current partition, not assign it
to DomU.Signed-off-by: Peng Fan
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Signed-off-by: Frank Li
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The iMX7ULP B0 chip has added more pins for muxing USB ID. The A3 board
follows it to exploit PTC13 for USB ID, so we don't need to use GPIO
any longer. The USB driver can recognize the USB mode from USB PHY.After this change, old boards with design using GPIO for USB mode won't
be supported.Signed-off-by: Ye Li
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Align the new pinfunc names with header file for all iMX7ULP EVK and ARM2
DTS files.
Also update the EVK DTS files to align with kernel for Rev A3
board. Removed the extcon node for USB ID, since A3 board uses USB ID pin
not GPIO.Signed-off-by: Ye Li
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i.MX7ULP B0 silicon has below updates in iomux
- GPIO function input buffer enable (IBE)/output buffer enable (OBE) is
now controlled by RGPIO module. IOMUXC IBE/OBE is used as an override.
- LPUART2_TX (I/O) to PTB12 (ALT4)
- LPUART2_RX (I) to PTB13 (ALT4)
- USB0_ID (I) to PTC13 (ALT11), PTC18 (ALT11) and PTC19 (ALT10)
- VIU_DE (I) to PTC18 (ALT12), PTC19 (ALT12) and PTE5 (ALT12)
- RTC_CLKOUT (O) to PTB5 (ALT11) and PTB14 (ALT11)
- SEC_VIO_B (I) to PTB4 (ALT11)
- Added new Input Selection Registers
PSMI1_USB0_ID Address: 0x40ac_0338 To select USB_ID input pad/source
PSMI1_VIU_DE Address: 0x40ac_033c To select VIU_DE input pad/sourceCopy the imx7ulp-pinfunc.h from latest kernel dts
(commit 18cdeadfe1967ea33d3bdfc7ccead6d6d06a98a6), and update
the mx7ulp-pins.h accordingly.Signed-off-by: Ye Li
29 Oct, 2018
2 commits
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Update API files generated from latest SCFW commit:
commit b5dbcf59157cf758da2b96c395e3f4cb2674437f
Author: Ranjani Vaidyanathan
Date: Sat Oct 27 02:04:47 2018 -0500SCF-248 Fix Linux boot fail on iMX8QX
Signed-off-by: Ye Li
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In flexspi driver, each sf command will disable the module in release bus
function. So reading from flexspi memory-map address using "md" command
can't work. When iMX8MM kicks M4 image to run flexspi NOR XIP,
this causes problem.Signed-off-by: Ye Li
27 Oct, 2018
1 commit
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enable CE_1 IOMUX setting for NAND on i.MX8MM EVK
Signed-off-by: Han Xu
26 Oct, 2018
2 commits
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Open configs to enable spl build for imx8q on both
Android and Android Auto.Change-Id: Ide757086ad0208973ac8510ba4a2f1c84aecdfad
Signed-off-by: Luo Ji -
Currently the clocks and power of USB controller and USB PHY are both
controlled by ehci-mx6 driver in device probe. However, the function
"ehci_usb_ofdata_to_platdata" calls "ehci_usb_phy_mode"
to access PHY registers when "dr_mode" is set to OTG, both "dr_mode" and
"extcon" properties are not set in DTB. This may cause hang at accessing
USB PHY registers if the power and clocks are not enabled.Change the usb type logic to more clear way:
1. plat->init_type: The requested USB mode type from uplayers
2. priv->init_type: The USB mode type specified by DTB or by the USB ID pin or
by external controller like tcpc or GPIO.
3. If two init_type are not same, return failure. Align with non-DM driver.
4. USB PHY access is moved after power and clock enabled.Signed-off-by: Ye Li
25 Oct, 2018
3 commits
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Update the RFSHCTL3 config for DDR4.
Signed-off-by: Bai Ping
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Add DDR3 init codes, board codes, defconfig and DTS into u-boot.
Basic modules are ready: SD, UART, I2C, USB host and NAND.There is a FPGA on this board. It controls WDOG_B, and ENET PHY RESET.
So reset and ethernet won't work at default.Signed-off-by: Ye Li
Acked-by: Peng Fan -
Added two DRAM PLL frequencies 266Mhz and 167Mhz output support.
Signed-off-by: Ye Li
24 Oct, 2018
1 commit
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Found the imx8mq Rev A chip (B0 and B1 chips are ok) boot hang at CAAM RNG init.
The jobring 0 can't complete instantiation descriptor and spins on checking ORSFR_JR0.In current implementation, the descriptor and jobring input and output base address locate
on TCM, because the driver uses raw_data array in jr_data_st structure as the buffer.
This seems cause the issue. If switched from TCM to OCRAM, the issue will go.Since accessing TCM by CAAM is not very reliable. Add this patch to use OCRAM for SPL case.
The early malloc is ready on SPL before calling board_init_f. So we can use malloc to allocate
memory instead of the raw_data array.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
23 Oct, 2018
5 commits
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When domu-init-ignore-poweroff set to yes, initially not power off
resources owned by DomU.When supporting M4 + Android Auto, M4 and Android Auto shared display,
but currently no partition created in M4 for display, so
scu_rm will power off the display and cause android auto error.
Let ignore power off first.Signed-off-by: Peng Fan
Reviewed-by: Ye Li -
Stop the usb device controller before enter kernel, this is required
to make kernel can properly init usb controller with it's in stopped
state.Suggested-by: Ye.Li
Reviewed-by: Ye Li
Signed-off-by: Li Jun -
Add HABv4 documentation for u-boot-dtb.imx targets covering the
following topics:- How to sign an securely boot an u-boot-dtb.imx image.
- How to extend the root of trust for additional boot images.
- Add 3 CSF examples.
- Add IVT generation script example.Reviewed-by: Ye Li
Reviewed-by: Utkarsh Gupta
Signed-off-by: Breno Lima -
The HABv4 is supported in i.MX 50, i.MX 53, i.MX 6, i.MX 7,
series and i.MX 8M, i.MX8MM devices.Add an introductory document containing the following topics:
- HABv4 Introduction
- HABv4 Secure Boot
- HABv4 Encrypted Boot
- HAB PKI tree generation
- HAB Fast Authentication PKI tree generation
- SRK Table and SRK Hash generationReviewed-by: Ye Li
Reviewed-by: Utkarsh Gupta
Signed-off-by: Breno Lima -
It is highly recommended to set the PRIBLOB bitfield to 0x3 once your
encrypted boot image has booted up, this prevents the generation of new
blobs that can be used to decrypt an encrypted boot image. The PRIBLOB is
a sticky type bit and cannot be changed until the next power on reset.Add the set_priblob_bitfield U-Boot command to prevent the generation of
new blobs.Signed-off-by: Clement Le Marquis
Acked-by: Ye Li
18 Oct, 2018
3 commits
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chunk_data_sz = sparse_header->blk_sz * chunk_header->chunk_sz;
All is uint32. chunk_data_sz may be bigger than 4G.Change chunk_data_sz to 64bit.
force chunk_header->chunk_sz and sparse_header->blk_sz to 64bit.Signed-off-by: Frank Li
Acked-by: Ye Li -
According to iMX8MM datasheet (IMX8MMIEC_Rev_D and IMX8MMCEC_Rev_D),
the speed grading for imx8mm is 800Mhz, 1.2Ghz, 1.6Ghz and 1.8Ghz.
Update them to get_cpu_speed_grade_hz function.Signed-off-by: Ye Li
Reviewed-by: Peng Fan -
Power down the A53 cores for dual core and single core iMX8MM parts
to save power.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
17 Oct, 2018
2 commits
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According the part type, delete A53 cores' nodes and disable VPU
decoder/encoder nodes from kernel DTB.Signed-off-by: Ye Li
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iMX8MM family has several variant parts below.
Add CPU type and relevant updatesi.MX 8M Mini Quad Full featured, 4x A53
i.MX 8M Mini QuadLite No VPU, 4x A53
i.MX 8M Mini Dual Full featured, 2x A53
i.MX 8M Mini DualLite No VPU, 2x A53
i.MX 8M Mini Solo Full featured, 1x A53
i.MX 8M Mini SoloLite No VPU, 1x A53Signed-off-by: Ye Li
16 Oct, 2018
4 commits
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Add support for FIT image loading of ATF and uboot proper for iMX8QXP mek.
Signed-off-by: Abel Vesa
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Add support for FIT image loading of ATF and uboot proper for iMX8QM mek.
Signed-off-by: Abel Vesa
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If SPL is built with CONFIG_SPL_LOAD_FIT make the checking for
FIT image. If there is no FIT image go with the raw default mode.Signed-off-by: Abel Vesa
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Since commit 8891410c729b ("MLK-19848 mx6dq: Fix chip version issue for
rev1.3") it's not possible to call the HAB API functions on i.MX6DQ
SoC Rev 1.3:Authenticate image from DDR location 0x12000000...
undefined instruction
pc : [] lr : []
reloc pc : [] lr : []
sp : 8ef444a8 ip : 126e8068 fp : 8ff59aa8
r10: 8ffd51e4 r9 : 8ef50eb0 r8 : 006e8000
r7 : 00000000 r6 : 126ea01f r5 : 0000002b r4 : 126e8000
r3 : 412c00dd r2 : 00000001 r1 : 00000001 r0 : 00000063
Flags: nzCv IRQs off FIQs off Mode SVC_32
Resetting CPU ...resetting ...
The hab.h code is defining the HAB API base address according to the
old SoC revision number, thus failing when calling the HAB API
authenticate_image() function.Fix this issue by using mx6dq rev 1.3 instead of mx6dq rev 1.5.
Signed-off-by: Breno Lima
Reviewed-by: Ye Li
12 Oct, 2018
2 commits
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Update the refresh_mode setting. Clear the RFSHCTL3.refresh_mode bit
to set it to normal_mode.Signed-off-by: Bai Ping
Reviewed-by: Ye Li -
Update the DDR4 MR value on i.MX8MM DDR4 EVK board.
Signed-off-by: Bai Ping
Reviewed-by: Ye Li