Eric Lee / smarc-uboot

08 Mar, 2010

1 commit

  • 6895d4510   Add support for KARO TX25 board ... Browse Code »

    This is an i.MX25 base board with only NAND
    so it uses nand_spl to boot.

    Signed-off-by: John Rigby

    Tune configuration, add support for (redundant) environment in NAND.
    Signed-off-by: Wolfgang Denk

    Acked-by: Wolfgang Denk
    CC: Fred Fan
    CC: Tom

    John Rigby
     

03 Mar, 2010

1 commit

  • fe389da6a   mpc83xx: fix out-of-tree mpc8315 nand build ... Browse Code »

    commit 2e95004deb6e33e33bf1b8a92a38cd2115bac4c2 "mpc83xx: Add NAND boot support
    for MPC8315E-RDB boards" symlinked nand_spl/board/freescale/mpc8315erdb to
    mpc8313erdb in order to not duplicate code.

    Since the main makefile builds nand_spl/board/$(BOARDDIR) (which makes sense),
    and the board Makefile and linker script are the only two necessary files
    to enable out-of-tree building, and other boards have duplicated nand makefiles
    (e.g. 8536ds & 8569mds), it only seems prudent to copy these two files in the
    name of the 8315 too.

    Signed-off-by: Kim Phillips
    Cc: Anton Vorontsov
    Cc: Wolfgang Denk

    Kim Phillips
     

28 Jan, 2010

2 commits

05 Nov, 2009

1 commit

27 Oct, 2009

2 commits

16 Oct, 2009

1 commit

01 Oct, 2009

1 commit

30 Sep, 2009

1 commit

  • 9a1a0aedb   NAND boot: MPC8536DS support ... Browse Code »

    MPC8536E can support booting from NAND flash which uses the
    image u-boot-nand.bin. This image contains two parts: a 4K
    NAND loader and a main U-Boot image. The former is appended
    to the latter to produce u-boot-nand.bin. The 4K NAND loader
    includes the corresponding nand_spl directory, along with the
    code twisted by CONFIG_NAND_SPL. The main U-Boot image just
    like a general U-Boot image except the parts that included by
    CONFIG_SYS_RAMBOOT.

    When power on, eLBC will automatically load from bank 0 the
    4K NAND loader into the FCM buffer RAM where CPU can execute
    the boot code directly. In the first stage, the NAND loader
    copies itself to RAM or L2SRAM to free up the FCM buffer RAM,
    then loads the main image from NAND flash to RAM or L2SRAM
    and boot from it.

    This patch implements the NAND loader to load the main image
    into L2SRAM, so the main image can configure the RAM by using
    SPD EEPROM. In the first stage, the NAND loader copies itself
    to the second to last 4K address space, and uses the last 4K
    address space as the initial RAM for stack.

    Obviously, the size of L2SRAM shouldn't be less than the size
    of the image used. If so, the workaround is to generate another
    image that includes the code to configure the RAM by SPD and
    load it to L2SRAM first, then relocate the main image to RAM
    to boot up.

    Signed-off-by: Mingkai Hu
    Signed-off-by: Kumar Gala

    Mingkai Hu
     

28 Sep, 2009

1 commit

11 Sep, 2009

1 commit

  • d1c3b2752   ppc4xx: Big cleanup of PPC4xx defines ... Browse Code »

    This patch cleans up multiple issues of the 4xx register (mostly
    DCR, SDR, CPR, etc) definitions:

    - Change lower case defines to upper case (plb4_acr -> PLB4_ACR)
    - Change the defines to better match the names from the
    user's manuals (e.g. cprpllc -> CPR0_PLLC)
    - Removal of some unused defines

    Please test this patch intensive on your PPC4xx platform. Even though
    I tried not to break anything and tested successfully on multiple
    4xx AMCC platforms, testing on custom platforms is recommended.

    Signed-off-by: Stefan Roese

    Stefan Roese
     

22 Aug, 2009

2 commits

  • 1aada9cd6   Fix all linker scripts for older binutils versions (pre-2.16) ... Browse Code »

    Commit f62fb99941c6 fixed handling of all rodata sections by using a
    wildcard combined with calls to ld's builtin functions SORT_BY_ALIGNMENT()
    and SORT_BY_NAME(). Unfortunately these functions were only
    introduced with biunutils version 2.16, so the modification broke
    building with all tool chains using older binutils.

    This patch makes it work again. This is done by omitting the use of
    these functions for such old tool chains. This will result in
    slightly larger target binaries, as the rodata sections are no longer
    in optimal order alignment-wise which reauls in unused gaps, but the
    effect was found to be insignificant - especially compared to the fact
    that you cannot build U-Boot at all in the current state.

    As ld seems to have no support for conditionals we run the linker
    script through the C preprocessor which can be easily used to remove
    the unwanted function calls.

    Note that the C preprocessor must be run with the "-ansi" (or a
    "-std=") option to make sure all the system-specific predefined
    macros outside the reserved namespace are suppressed. Otherise, cpp
    might for example substitute "powerpc" to "1", thus corrupting for
    example "OUTPUT_ARCH(powerpc)" etc.

    Signed-off-by: Wolfgang Denk
    Cc: Mike Frysinger

    Wolfgang Denk
     
  • 269610f6b   NAND boot: fix nand_load overlap issue ... Browse Code »

    The code copy data from NAND flash block by block, so when
    the data length isn't a whole-number multiple of the block
    size, it will overlap the rest space.

    Signed-off-by: Mingkai Hu
    Signed-off-by: Scott Wood

    Mingkai Hu
     

30 Jul, 2009

1 commit

  • 82a7edc7e   ppc4xx: Canyonlands-NAND-boot: Support 2 Crucial 512MByte SODIMM's ... Browse Code »

    Some Canyonlands boards are equipped with different SODIMM's. This is no
    problem with the "normal" NOR booting Canyonlands U-Boot, since it
    automatically detects the SODIMM's via SPD data and correctly configures
    them. But the NAND booting version is different. Here we only have 4k
    of image size to completely setup the hardware, including DDR2 setup.
    So we need to use a fixed DDR2 setup here. This doesn't work for different
    SODIMM's right now.

    Currently only this Crucial SODIMM is support:
    CT6464AC667.8FB (dual ranked)

    Now some boards are shipped with this SODIMM:
    CT6464AC667.4FE (single ranked)

    This patch now supports both SODIMM's by configuring first for the dual
    ranked DIMM. A quick shows, if this module is really installed. If this test
    fails, the DDR2 controller is re-configured for the single
    ranked SODIMM.

    Tested with those SODIMM's:

    CT6464AC667.8FB (dual ranked)
    CT6464AC667.4FE (single ranked)

    Signed-off-by: Stefan Roese

    Stefan Roese
     

17 Jul, 2009

1 commit

08 Jul, 2009

2 commits

  • 1dac3a518   nand_spl: Fix cmd_ctrl usage in nand_boot.c. ... Browse Code »

    When adding large page NAND support to this file, I had a misunderstanding
    about the exact semantics of NAND_CTRL_CHANGE (which isn't documented
    anywhere I can find) -- it is apparently just a hint to drivers,
    which aren't required to preserve the old value for subsequent
    non-"change" invocations.

    This change makes nand_boot.c no longer assume this. Note that this
    happened to work by chance with some NAND drivers, which don't preserve
    the value, but treat 0 equivalently to NAND_CTRL_ALE.

    I don't have hardware to test this, so any testing is appreciated.

    Signed-off-by: Scott Wood

    Scott Wood
     
  • b74ab7373   nand_spl: read environment early, when booting from NAND using nand_spl ... Browse Code »

    Currently, when booting from NAND using nand_spl, in the beginning the default
    environment is used until later in boot process the dynamic environment is read
    out. This way environment variables that must be interpreted early, like the
    baudrate or "silent", cannot be modified dynamically and remain at their
    default values. Fix this problem by reading out main and redundand (if used)
    copies of the environment in the nand_spl code.

    Signed-off-by: Guennadi Liakhovetski
    Signed-off-by: Scott Wood

    Guennadi Liakhovetski
     

07 Jul, 2009

1 commit

21 Jun, 2009

1 commit

  • 40c642bc1   MX31: Add NAND SPL for i.MX31. ... Browse Code »

    This patch adds the NAND SPL framework needed to boot i.MX31 boards
    from NAND.

    It has been tested on a i.MX31 PDK board with large page NAND. Small
    page NANDs should work as well, but this has not been tested.

    Note: The i.MX31 NFC uses a non-standard layout for large page NANDs,
    whether this is compatible with a particular setup depends on how
    the NAND device is programmed by the flash programmer (e.g. JTAG
    debugger).

    The patch is based on the work by Maxim Artamonov.

    Signed-off-by: Maxim Artamonov
    Signed-off-by: Magnus Lilja

    Magnus Lilja
     

16 May, 2009

1 commit

21 Mar, 2009

1 commit

  • f62fb9994   Fix all linker script to handle all rodata sections ... Browse Code »

    A recent gcc added a new unaligned rodata section called '.rodata.str1.1',
    which needs to be added the the linker script. Instead of just adding this
    one section, we use a wildcard ".rodata*" to get all rodata linker section
    gcc has now and might add in the future.

    However, '*(.rodata*)' by itself will result in sub-optimal section
    ordering. The sections will be sorted by object file, which causes extra
    padding between the unaligned rodata.str.1.1 of one object file and the
    aligned rodata of the next object file. This is easy to fix by using the
    SORT_BY_ALIGNMENT command.

    This patch has not be tested one most of the boards modified. Some boards
    have a linker script that looks something like this:

    *(.text)
    . = ALIGN(16);
    *(.rodata)
    *(.rodata.str1.4)
    *(.eh_frame)

    I change this to:

    *(.text)
    . = ALIGN(16);
    *(.eh_frame)
    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))

    This means the start of rodata will no longer be 16 bytes aligned.
    However, the boundary between text and rodata/eh_frame is still aligned to
    16 bytes, which is what I think the real purpose of the ALIGN call is.

    Signed-off-by: Trent Piepho

    Trent Piepho
     

09 Mar, 2009

1 commit

29 Jan, 2009

1 commit

28 Jan, 2009

1 commit

  • 2b6fd5c77   mpc83xx: fix undefined reference to `flush_cache' error in simpc8313 build ... Browse Code »

    extend commit c70564e6b1bd08f3230182392238907f3531a87e
    "NAND: Fix cache and memory inconsistency issue" to add the cache.o dependency
    to the simpc8313 build and fix this:

    ...Large Page NAND...Configuring for SIMPC8313 board...
    nand_boot_fsl_elbc.o: In function `nand_boot':
    nand_spl/board/sheldon/simpc8313/nand_boot_fsl_elbc.c:150: undefined reference to `flush_cache'
    make[1]: *** [/home/r1aaha/git/u-boot-mpc83xx/nand_spl/u-boot-spl] Error 1
    make: *** [nand_spl] Error 2

    Signed-off-by: Kim Phillips

    Kim Phillips
     

27 Jan, 2009

1 commit

24 Jan, 2009

3 commits

  • 833d94bcd   Merge branch 'next' Browse Code »
    Kim Phillips
     
  • 5bb907a49   mpc83xx: New board support for SIMPC8313 ... Browse Code »

    This patch will create a new board, SIMPC8313, from Sheldon Instruments. This
    board boots from NAND devices and is configureable for either large or small
    page devices. The board supports non-soldered DDR2, one ethernet port, a
    Marvell 88E1118 PHY, and PCI host support. The board also has a FPGA connected
    to the eLBC providing glue logic to a TMS320C67xx DSP.

    Signed-off-by: Ron Madrid
    Signed-off-by: Kim Phillips

    Ron Madrid
     
  • c70564e6b   NAND: Fix cache and memory inconsistency issue ... Browse Code »

    We load the secondary stage u-boot image from NAND to
    system memory by nand_load, but we did not flush d-cache
    to memory, nor invalidate i-cache before we jump to RAM.
    When the system has cache enabled and the TLB/page attribute
    of system memory is cacheable, it will cause issues.

    - 83xx family is using the d-cache lock, so all of d-cache
    access is cache-inhibited. so you can't see the issue.
    - 85xx family is using d-cache, i-cache enable, partial
    cache lock. you will see the issue.

    This patch fixes the cache issue.

    Signed-off-by: Dave Liu
    Signed-off-by: Scott Wood

    Dave Liu
     

19 Nov, 2008

1 commit

  • 9b827cf17   Align end of bss by 4 bytes ... Browse Code »

    Most of the bss initialization loop increments 4 bytes
    at a time. And the loop end is checked for an 'equal'
    condition. Make the bss end address aligned by 4, so
    that the loop will end as expected.

    Signed-off-by: Selvamuthukumar
    Signed-off-by: Wolfgang Denk

    Selvamuthukumar
     

30 Oct, 2008

1 commit

  • 4e190b03a   Make Freescale local bus registers available for both 83xx and 85xx. ... Browse Code »

    - Rename lbus83xx_t to fsl_lbus_t and move it to asm/fsl_lbc.h so that it
    can be shared by both 83xx and 85xx
    - Remove lbus83xx_t and replace it with fsl_lbus_t in all 83xx boards
    files which use lbus83xx_t.
    - Move FMR, FIR, FCR, FPAR, LTESR from mpc83xx.h to asm/fsl_lbc.h so that
    85xx can share them.

    Signed-off-by: Jason Jin
    Signed-off-by: Haiying Wang
    Signed-off-by: Scott Wood

    Haiying Wang
     

19 Oct, 2008

1 commit

31 Aug, 2008

1 commit

  • 11edcfe26   ARM: Add support for S3C6400 based SMDK6400 board ... Browse Code »

    SMDK6400 can only boot U-Boot from NAND-flash. This patch adds a nand_spl
    driver for it too. The board can also boot from the NOR flash, but due to
    hardware limitations it can only address 64KiB on it, which is not enough
    for U-Boot. Based on the original sources by Samsung for U-Boot 1.1.6.

    Signed-off-by: Guennadi Liakhovetski

    Guennadi Liakhovetski
     

22 Aug, 2008

1 commit

14 Aug, 2008

1 commit

13 Aug, 2008

4 commits

30 Jul, 2008

1 commit