27 Apr, 2018
40 commits
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Some dwc3 based USB3 IP may have a wrong default suspend clk
setting, so add an interface to correct it by board setting.Acked-by: Peng Fan
Signed-off-by: Li Jun
(cherry picked from commit 240b636718313e03db505a713e66e3f893cb7727) -
Add an simple driver for USB typec port controller in freescale common codes.
The functionalities in this driver include:1. Support to set UFP mode, when running as device mode, the
board level codes can use it to configure the TCPC port to UFP mode.2. Support to set DFP mode for USB host.
3. Support PD charge with setup PD connection and send/receive PD messages
to negotiate a proper voltage and current.4. Support power source with 2 stages of capability. Some power delivery source
send the source capability by 2 stages: 1st stage send the source capability
message with only basic 5V PDO, after the 5V power session setup, 2nd stage
it will send full source capabilities with all PDOs it can support, in this
case, we should go on to process the following PD source cap to have a new
power session setup.Signed-off-by: Li Jun
Signed-off-by: Ye Li -
Print out atf commit in U-Boot.
Signed-off-by: Peng Fan
(cherry picked from commit df89948806c38e38119767a67ef0e18f24ac886b) -
Need to pass total 5 arguments for SIP HAB call on i.MX8MQ, so
update the interface to add new argument.Signed-off-by: Ye Li
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We found USB issue when using super-speed for mfgtool, temporally work around
the problem to use high-speed only.Signed-off-by: Ye Li
Reviewed-by: Li Jun
(cherry picked from commit e31f99c05c37ac35080e415cfd8c8e2a1c96f865) -
When booting for mfgtool, we need to disable DCSS and HDMI since the HDMI
firmware won't be loaded by mfgtool. Add the detect in u-boot and update the
DTB.Signed-off-by: Ye Li
Acked-by: Peng Fan
(cherry picked from commit 1d01cec0296d56ba8436941864d8da81013e0732) -
Add board level codes and build config for i.MX8MQ EVK board.
Support SPL to initialize the DDR and load u-boot.Signed-off-by: Ye Li
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Update the DTSi and add imx8mq-evk DTS file from v2017.03.
The MMC alias are removed to fix MMC device index problem.Signed-off-by: Ye Li
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Signed-off-by: Ye Li
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We will use watch dog to reset system for i.MX8MQ not through the PSCI.
Build watchdog driver for imx8mq.Signed-off-by: Ye Li
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Refine mmu table. Map TCML/TCMU as non-cachable.
Signed-off-by: Peng Fan
Signed-off-by: Ye Li -
On i.MX8MQ, eMMC is on USDHC0 while SD is on USDHC1. To support boot from
both ports, return different BOOT_DEVICE_MMC devices for each port.
Additional, when boot from eMMC, SPL needs to switch to boot partition for
image loading, have to ensure MMCSD_MODE_EMMCBOOT is used for eMMC port.Signed-off-by: Ye Li
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The i.MX8M reuses the QSPI controller from i.MX7D. Add the CONFIG_IMX8M
define to the driver.Signed-off-by: Ye Li
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Allow be omited by DM
Signed-off-by: Peng Fan
(cherry picked from commit cbe93dc60b64072d4b945c7634c6ed3560a2ec77) -
Allow the dm driver be omited by SPL.
Fix wrong config name for pfuze100 regulator.Signed-off-by: Peng Fan
Signed-off-by: Ye Li -
add dependency for CONFIG_SYS_I2C_MXC
Signed-off-by: Peng Fan
(cherry picked from commit cc88d9708a38e82073bfa3ecde3f329a7103b0ff) -
Add i.mx8m pinctrl driver.
Signed-off-by: Peng Fan
(cherry picked from commit 70e17c13b99ae41f416b5c72c364a0e4483188e8) -
The formal production name starts with imx, so change relevant names
in codes to use this prefix.Signed-off-by: Ye Li
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To support the trust boot chain, we integrate the authentication
into the kernel image loading process. The kernel image will be verified
at its load address. So when signing the kernel image, we need to
use this load address which may change on different platforms.Signed-off-by: Ye Li
(cherry picked from commit 3c118b8d6bbe1a25ca8c8bafeb528309f16fc73d)
(cherry picked from commit fd9a9759ed9b3a9fc26b18aff00880382213b1ca) -
When loading kernel image, the image size is parsed from header, so it
does not include the CSF and IVT.Add back the authenticate_image function to wrap the imx_hab_authenticate_image
with calculating IVT offset and full image size.Signed-off-by: Ye Li
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Since the u-boot size increases after using OF_CONTROL to including DTB,
we have to adjust ENV_OFFSET to 896K for SD/eMMC/FLASH.Signed-off-by: Ye Li
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Change USDHC0 and USDHC1 per clock source from APLL_PFD1,
and set the APll_PFD1 clock rate to 352.8MHz.Also gate off APll_PFD1/2/3 before boot OS, otherwise set
the clock rate of APll_PFD1/2/3 during OS boot up will triger
some warning message.Reviewed-by: Ye Li
Signed-off-by: Haibo Chen
(cherry picked from commit 07ef0fab23204684d82f27baf721a72b247f30c5) -
Since commit 6e1f4d2652e79 ("arm: imx-common: add SECURE_BOOT option
to Kconfig") it's preferable to select CONFIG_SECURE_BOOT via Kconfig.Add ARCH_MX7ULP as a CONFIG_SECURE_BOOT dependency, do not select
CONFIG_FSL_CAAM since CAAM is not implemented for i.MX7ULP yet.Signed-off-by: Breno Lima
Reviewed-by: Ye Li
(cherry picked from commit d4c01cd3f6f5ba59ca17ebf52f610f629895ac7a) -
On i.MX7ULP B0, the DDR clock target is increased from 320Mhz to 380Mhz.
We update DDR clock relevant settings to approach the target. But since the
limitation on LCDIF pix clock for HDMI output
(refer commit dba948539edd4611610d9f1fc3711d1d922262ae), we set DDR clock to
352.8Mhz (25.2Mhz * 14) by using the clock path:APLL PFD0 -> DDR CLK -> NIC0 -> NIC1 -> LCDIF clock
To reduce the impact to entire system, the NIC0_DIV and NIC1_DIV are kept,
so the divider 14 is calculated as:
14 = (NIC0_DIV + 1) * (NIC1_DIV + 1) * (LCDIF_PCC_DIV + 1)NIC0_DIV: 1
NIC1_DIV: 0
LCDIF_PCC_DIV: 6APLL and APLL PFD0 settings:
PFD0 FRAC: 27
APLL MULT: 22
APLL NUM: 1
APLL DENOM: 20This patch applies the new settings for both DCD and plugin.
There is no DDR script change on this new frequency.
Overnight memtester is passed.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit a48daae2d43cb0415ad8b3cfca0f6d064ac6cd74) -
On i.MX7ULP B0, there is change in NIC clock dividers architecture.
On A0, the NIC1 BUS and EXT dividers were in a chain with NIC1 DIV, but
on B0 they are parallel with NIC1 DIV. So now the dividers are independent.
This patch modifies the scg_nic_get_rate function according to this change.Signed-off-by: Ye Li
Acked-by: Peng Fan
(cherry picked from commit 1a53e025c6be73a84570a3857cb709d98e49ef96) -
The normal target frequency for ULP A7 core is 500Mhz, but now ROM
set the core frequency to 413Mhz. So change it to 500Mhz in u-boot.Signed-off-by: Ye Li
(cherry picked from commit 4f822410518cd5847f8621d66c3e3b2599145b9e) -
Due to the APLL out glitch issue TKT332232, the APLLCFG PLLS bit must be set
to select SCG1 APLL PFD for generating system clock to align with the design.Signed-off-by: Ye Li
Acked-by: Peng Fan
(cherry picked from commit 242823400c5bd59960e1b40d941e177e8ebad57e) -
Since there is no register for CPU revision, we use ROM version to
check the A0 or B0 chip.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit 9ad30c8439ece3a8b88040847155405fca40facf) -
Add back the defconfig to boot M4 in single mode, because some customers
are using the defconfig during development.Signed-off-by: Ye Li
Acked-by: Peng Fan
(cherry picked from commit ad2298d04fe2443e2b60114001523555d0cd5a50) -
To support HDMI display on EVK board, the LCDIF pix clock must be 25.2Mhz. Since
the its PCC divider range is from 1-8, the max rate of LCDIF PCC source clock is
201.6Mhz. This limits the source clock must from NIC1 bus clock or NIC1 clock, other sources
from APLL PFDs are higher than this max rate.The NIC1 bus clock and NIC1 clock are from DDRCLK whose parent source is APLL PFD0, so we must
change the APLL PFD0 and have impact to DDRCLK, NIC1 and NIC1 bus.Eventually, this requests to set the APLL PFD0 frequency to 302.4Mhz (25.2 * 12),
with settings:PFD0 FRAC: 32
APLL MULT: 22
APLL NUM: 2
APLL DENOM: 5Signed-off-by: Ye Li
Tested-by: Fancy Fang
(cherry picked from commit 91be2789a93288cc087cd9e8db522c8308ef007c)
(cherry picked from commit dba948539edd4611610d9f1fc3711d1d922262ae) -
The GPU uses APLL PFD2 as its clock parent (483.84Mhz) with divider set to 1.
This frequecy is out of ULP A0 spec. The MAX rate for GPU is 350Mhz.
So we simply configure the APLL PFD2 to 345.6Mhz (FRAC=28) to workaround the problem.
The correct fix should let GPU handle the clock rate in kernel.Signed-off-by: Ye Li
(cherry picked from commit e931d534fd68e0e639082766de17a20e705fd908)
(cherry picked from commit e72f766c98a3df9b620feb51484e33c7d50bed3c) -
The num/denom is a float value, but in the calculation it is convert
to integer 0, and cause the result wrong.Signed-off-by: Ye Li
(cherry picked from commit 4a8f51499ca098637e9ee2036066374d34458865)
(cherry picked from commit 65e74eb0b354cb01c8422f30f9e14dead42201b9) -
Add environment variables for mfgtool.
Signed-off-by: Ye Li
(cherry picked from commit 2e79a95aad75eeb7d225caa77cc31deaaf8d4a29) -
Add the OCOTP driver and fuse command configurations.
Signed-off-by: Ye Li
(cherry picked from commit ab7ce08ea33342adee44f6a4de86a2c8b8ec993c) -
Add build configuration and DTS file to enable eMMC for eMMC reworked
EVK board.
Because the eMMC DTS file has QSPI node disabled, so we change to use
non-DM QSPI driver.Signed-off-by: Ye Li
(cherry picked from commit 9ae0e03eb829f694d26caec22f91d1f0fdba980d) -
Add board_late_mmc_env_init to support MMC device detection for environment
variables.Signed-off-by: Ye Li
(cherry picked from commit 6c2fe5b60692e7d0e86383c44792e5f2938bfa14) -
PTA and PTB banks are at M4 domain, but some boards like ARM2 use
them for controlling A7 domain modules. So we may need to support
them in GPIO driver.In the imx_rgpio2p driver, the non-DM driver supports full 6 GPIO
banks, with PTA from index 0. But the DM driver which uses DTB only
have 4 GPIO banks, with PTC from index 0.This will cause problem when using GPIO. So this patch add PTA and PTB
banks to DTB, and reorder the sequence for gpio with PTA from index 0.
So the non-DM driver and DM driver are aligned.Signed-off-by: Ye Li
(cherry picked from commit 0b4965271702d6a40047bd0c9b419dd007c03f35) -
Since we can use USB ethernet instead of local ethernet, add ethernet support
for it. To use USB ethernet function at u-boot, just plug in Micro-AB cable
at USBOTG1 port with USB2Ethernet adapter connected.Signed-off-by: Peter Chen
(cherry picked from commit 60ffddf87cf6b8502c5d5fc6540364adfd66ebb3)
Signed-off-by: Ye Li
(cherry picked from commit 63c2e1de37e1e24f35279f50efa5a330e2cb3d07) -
Enable and setup board level codes for MIPI DSI splashscreen on EVK board.
User needs set env variable"panel=HX8363_WVGA" for displaying.Signed-off-by: Ye Li
(cherry picked from commit 49cb68f5c17e42f9290336e1252ace6ac7d0b5ce)
(cherry picked from commit be3d3d5c140a1617c1ce35e8657f2d45bc8c70eb) -
Add the clocks functions for enabling LCDIF and DSI clocks.
Also add the arch_preboot_os to disable the video before enter into
the kernel.Signed-off-by: Ye Li
(cherry picked from commit a783799017a929f9918c9c5981fe3a7a25cd8125)
(cherry picked from commit fce3f6e59f6ae5a171bbb6581420712c4aaa14c3)