04 Aug, 2010
2 commits
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While running from flash, i. e. before relocation, we have only a
limited C runtime environment without writable data segment. In this
phase, some configurations (for example with environment in EEPROM)
must not use the normal getenv(), but a special function. This
function had been called getenv_r(), with the idea that the "_r"
suffix would mean the same as in the _r_eentrant versions of some of
the C library functions (for example getdate vs. getdate_r, getgrent
vs. getgrent_r, etc.).Unfortunately this was a misleading name, as in U-Boot the "_r"
generally means "running from RAM", i. e. _after_ relocation.To avoid confusion, rename into getenv_f() [as "running from flash"]
Signed-off-by: Wolfgang Denk
Acked-by: Detlev Zundel
02 Aug, 2010
1 commit
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doing so helps avant garde users, such as those using simulators that
allow users to configure the number of cores, so as to not have to
manually adjust u-boot sources. h/w should also be reliably setting
FRR NCPU in the future.Signed-off-by: Kim Phillips
Signed-off-by: Kumar Gala
30 Jul, 2010
1 commit
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Signed-off-by: Mike Frysinger
27 Jul, 2010
12 commits
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Changes for P2020DS DDR applies to other 8xxx platform
Signed-off-by: York Sun
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Enabled registered DIMMs using data from SPD. RDIMMs have registers
which need to be configured before using. The register configuration
words are stored in SPD byte 60~116 (JEDEC standard No.21-C). Software
should read those RCWs and put into DDR controller before initialization.Signed-off-by: York Sun
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For 85xx silicon which supports address hashing, it can be activated by
hwconfig.Signed-off-by: York Sun
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Previous code presumes each DIMM has up to two rank (chip select). Newer
DDR controller supports up to four chip select on one DIMM.Signed-off-by: York Sun
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Verified on MPC8641HPCN with four DDR2 dimms. Each dimm has dual
rank with 512MB each rank.Also check dimm size and rank size for memory controller interleaving
Signed-off-by: York Sun
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Replace environmental variables memctl_intlv_ctl and ba_intlv_ctl with
hwconfig parameters. The syntax issetenv hwconfig "fsl_ddr:ctlr_intlv=,bank_intlv="
The mode values for memory controller interleaving are
cacheline
page
bank
superbankThe mode values for bank interleaving are
cs0_cs1
cs2_cs3
cs0_cs1_and_cs2_cs3
cs0_cs1_cs2_cs3Signed-off-by: York Sun
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Signed-off-by: Kumar Gala
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Signed-off-by: Scott Wood
Signed-off-by: Emil Medve
Signed-off-by: Ed Swarthout
Signed-off-by: Kumar Gala -
Add support for initializing the SERDES blocks on CoreNet style QoriQ
devices and the p4080 specific SERDES tables to know which actual
componetns are enabled.Additionally, split out the Frame Manger (FMAN) into its specific ethernet
ports instead of gross level of the full FMAN.Signed-off-by: Li Yang
Signed-off-by: Roy Zang
Signed-off-by: Kumar Gala -
On the new QorIQ/CoreNet based platforms we need to initialize the
"portals" as access into the Data Path subystem as well as Logical IO
Device Numbers (LIODN) that are used for the IOMMU (PAMU).Signed-off-by: Kumar Gala
Signed-off-by: Scott Wood
Signed-off-by: Kim Phillips
Signed-off-by: Kumar Gala -
The CoreNet style platforms can have a L3 cache that fronts the memory
controllers. Enable that cache as well as add information into the
device tree about it.Signed-off-by: Kumar Gala
Signed-off-by: Dave Liu
Signed-off-by: Becky Bruce
Signed-off-by: Roy Zang
Signed-off-by: Timur Tabi
Signed-off-by: Kumar Gala -
If 36-bit physical address is used, move the INIT_RAM_ADDR to higher
address. This frees the low 4GB address space for better use.Signed-off-by: York Sun
26 Jul, 2010
5 commits
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Add basic structures for Frame Manager on P4080/P3041/P5020 devices
Signed-off-by: Kumar Gala
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* Added PCIE4 address, offset, DEVDISR & LAW target ID
* Added new p4080 DDR registers and defines to immap
* Add missing corenet platform DEVDISR related defines
* Updated ccsr_gur to include LIODN registers
* Add RCWSR defines
* Added Basic qman, pme, bman immap structs
* Added SATA related offsets & addresses
* Added Frame Manager 1/2 offsets & addresses
* Renamed CONFIG_SYS_TSEC1_OFFSET to CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET
* Added various offsets and addresses that where missingSigned-off-by: Kumar Gala
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Serial devices currently have to manually stuff \r after every \n found,
but this is a bit more difficult with the jtag console since we process
everything in chunks of 4 bit. So we have to scan & stuff the whole
string rather than what most serial drivers do which is output on a byte
per byte basis.Signed-off-by: Mike Frysinger
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While we're in here, add some useful debug points. We need custom debug
statements because we need the output to only go to the serial port. If
we used the standard debug helpers, the output would also go to the stdout
(which would be the jtag console) and make it hard to figure out what is
going where exactly.Signed-off-by: Mike Frysinger
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If the other side isn't listening, we should reset the state to ignore
the whole message and not just the part we missed. This makes it easier
to connect at any time to the jtag console without worrying about the two
sides getting out of sync and thus sending garbage back and forth.Signed-off-by: Mike Frysinger
25 Jul, 2010
2 commits
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Lots of code use this construct:
cmd_usage(cmdtp);
return 1;Change cmd_usage() let it return 1 - then we can replace all these
ocurrances byreturn cmd_usage(cmdtp);
This fixes a few places with incorrect return code handling, too.
Signed-off-by: Wolfgang Denk
23 Jul, 2010
5 commits
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Signed-off-by: Stefan Roese
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This patch adds the "ecctest" command to test and simulate ECC errors
(single bit and/or double bit) while running from SDRAM. Currently only
the IBM DDR2 controller is supported (405EX, 440SP(e), 460EX/GT).This is done by copying and calling functions, modifying the SDRAM
controller operation mode, in internal SRAM/OCM.For correctable ECC errors (single bit) only the status will be printed
since the DDR2 controller doesn't provide the faulting address:=> ecctest 1000000 1
Using address 01000000 for 1 bit ECC error injection
ECC: Correctable errorUncorrectable ECC errors (double bit) will also display the faulting
address:=> ecctest 1000000 2
Using address 01000000 for 2 bit ECC error injection
ECC: Uncorrectable error at 0x0001000000To enable this "ecctest" function you need to define CONFIG_CMD_ECCTEST
in the board config header.Tested on katmai and t3corp.
Signed-off-by: Stefan Roese
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Use the correct macro instead of the hardcoded 0x4c to clear the ECC
status in the 440/460 DDR(2) error status register after ECC
initialization.Also the non-440 parts (405EX(r) right now) and the IBM DDR PPC variants
(440GX) use a different registers to clear this error status. Use the
correct ones.Signed-off-by: Stefan Roese
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Make sure that some SDRAM/DDR2 registers are only defined for the PPC
variants really implementing those registers.Signed-off-by: Stefan Roese
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Using this define, a board can define an opimized RFDC value and use
the auto calibration code to "tune" the remaining DDR2 controller
calibration register.Signed-off-by: Stefan Roese
21 Jul, 2010
2 commits
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Move serdes init until after we are in ram so we can keep track of a
global static protocal map for the particular serdes config we are in.
This makes is_serdes_configured() much simplier and not constantly
reading registers to determine if a given device is enabled based on the
protocol.Signed-off-by: Kumar Gala
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Move serdes init until after we are in ram so we can keep track of a
global static protocal map for the particular serdes config we are in.
This makes is_serdes_configured() much simplier and not constantly
reading registers to determine if a given device is enabled based on the
protocol.Signed-off-by: Kumar Gala
20 Jul, 2010
8 commits
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There are various locations that we have chip specific info:
* Makefile for which ddr code to build
* Added p3041 to cpu_type_list and SVR list
* Added number of LAWs for p3041
* Set CONFIG_MAX_CPUS to 4 for p3041Signed-off-by: Kumar Gala
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There are various locations that we have chip specific info:
* Makefile for which ddr code to build
* Added p5020 & p5010 to cpu_type_list and SVR list
* Added number of LAWs for p5020
* Set CONFIG_MAX_CPUS to 2 for p5020Signed-off-by: Kumar Gala
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The user manual refers to FMAN1 and FMAN2 not 0 and 1.
Signed-off-by: Emil Medve
Signed-off-by: Kumar Gala -
On QorIQ CoreNet based devices we have a global clocking block. We want
to keep track of SYSCLK frequency as it is what is used to derive all
other frequencies in the SoCSigned-off-by: Kumar Gala
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Move to using fdt_node_offset_by_compat_reg to find the node offsets we
want to update instead of using aliases.Signed-off-by: Kumar Gala
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Previously we used an alias the pci node to determine which node to
fixup or delete. Now we use the new fdt_node_offset_by_compat_reg to
find the node to update.Additionally, we replace the code in each board with a single macro call
that makes assumes uniform naming and reduces duplication in this area.Signed-off-by: Kumar Gala
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Remove dupliacted setting of PCI/PCIe address and offsets in board
config.h. Renamed CONFIG_SYS_PCI1/2_ADDR to CONFIG_SYS_PCI1/2ADDR on
MPC8641 boards since its really PCIE controllers and not PCI.Signed-off-by: Kumar Gala
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Remove dupliacted setting of PCI/PCIe address and offsets in board
config.h.Signed-off-by: Kumar Gala
18 Jul, 2010
1 commit
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The board maintainer states:
The GTH board is obsolete and has not been manufactured for
several years.
To my knowledge, no recent U-Boot build has been tested on that
card.So drop support for this board.
Signed-off-by: Wolfgang Denk
Cc: Thomas Lange
Acked-by: Thomas Lange
17 Jul, 2010
1 commit