24 May, 2016

1 commit


23 May, 2016

1 commit


16 May, 2016

1 commit

  • SNVS TAMPER pin and BOOT MODE pins are in SNVS IOMUXC module,
    not in IOMUXC, so correct the related registers' offset.

    Use IOMUX_CONFIG_LPSR flag for these pins, so we can differentiate
    them from iomuxc pins.

    Define CONFIG_IOMUX_LPSR for mx6ull_ddr3_arm2 board to enable
    using these pins.

    Signed-off-by: Peng Fan

    Peng Fan
     

11 May, 2016

1 commit


06 May, 2016

1 commit

  • Current environment offset on NAND is 37MB, this will cause a alignment
    issue when erasing if nand erase block is 2MB. The saveenv is failed.

    => saveenv
    Saving Environment to NAND...
    Erasing NAND...
    Attempt to erase non block-aligned data

    Since the max erase block we supported is 4MB, adjust the env offset to 60MB,
    where is the last 4MB in 64MB reserved area for boot.

    Signed-off-by: Ye Li

    Ye Li
     

21 Apr, 2016

1 commit

  • 1. Bind the macro CONFIG_MX6ULL_DDR3_ARM2_EMMC_REWORK to eMMC 8 bits rework, which
    conflicts with QSPIA and NAND, that we have to disable them at same time.

    2. Bind the macro CONFIG_MX6ULL_DDR3_ARM2_QSPIB_REWORK to QSPI B port rework, which
    conflicts with SD2 and NAND, that we have to disable them at same time.

    3. Fix a typo issue of CONFIG_MX6ULL_DDR3_ARM2_EMMC_REWORK

    4. Enable QSPI support for default SD boot case.

    Signed-off-by: Ye Li
    (cherry picked from commit 00f36b3e9445ff47ed68262ef2d656e410cd8fcd)

    Ye Li
     

13 Apr, 2016

1 commit


25 Mar, 2016

33 commits