22 May, 2020
1 commit
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Wrong variable is check during pcie driver removing (6QP is checked but
should be 6Q), so iMX6Q won't enter its handling and cause kernel PCI link
failed to detect.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit 0dd8cc03ecc45faaba0297c2832ff6ae307e8f30)
27 Apr, 2020
3 commits
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Update PCIE IMX DM driver supports iMX8QM/QXP and
iMX6QDL/QP/SX. Non-DM driver supports iMX6QDL/QP/SX.
The changes in DM parses cfg/mem/io ranges, gpios, regulators and
clocks (imx8 only) from DTS for RC mode, and set iATU mapping for
each regions.The original iATU mapping sets full PCI region to CFG space. iATU
translates MEM/IO TLP to CFG TLP when the address is falled into
the region.
The new mapping sets CFG/IO/MEM spaces to align with kernel like below
ATU region 0 for MEM access
ATU region 1 for CFG0 or CFG1 access by bus id
ATU region 2 for IO accessSigned-off-by: Ye Li
(cherry picked from commit eb0959cbf2118342a544440f124e0c81eeba70e3) -
Disable the LTSSM when link is down in uboot.
Otherwise, the pcie ep/rc validation system in kernel
would be impacted by the enabled ltssm stat in the uboot.Signed-off-by: Richard Zhu
Reviewed-by: Ye Li
(cherry picked from commit cdedbb42e052d4bb3ff6b45044dd0d6023f3cb20)
(cherry picked from commit dcad2189b3d4f405a4675c1cc4f9ce38b524a947) -
Enable pcie support in uboot on imx6sx sd boards
- enable_pcie_clock should be call before ssp_en is set,
since that ssp_en control the phy_ref clk gate, turn on
it after the source of the pcie clks are stable.
- add debug info
- add rx_eq of gpr12 on imx6sx
- there are random link down issue on imx6sx. It's
pcie ep reset issue.
solution:reset ep, then retry link can fix it.(cherry picked from commit ec78595a24b5ff1020baa97b6d6e79a3a3326307)
Signed-off-by: Richard Zhu
Signed-off-by: Ye Li
(cherry picked from commit 81fd30250110d72992758f08b66c07306126892b)
(cherry picked from commit 4226ce46f24e176dcfc20aea1af0713b4b425655)
(cherry picked from commit 3e1a0a7f37d749d5e36e27ad46e8c8db12a865be)
23 Apr, 2020
1 commit
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- one lane pcie gen2 link is okay, the cfg space
of the rc/ep can be accessed.
rc cfg base 0x5f00_0000. ep cfg base 0x6000_0000
- limit to gen2 speed
- mask the wait of eq3 finish, because it is used
for gen3.
- use pcie_ctrla_init_rc() to do the initialization
of the pciea controller
- setup the common pcie codes in pcie_imx8x.c, separate
the different soc speicifed initialization codes into
their own pcie/board codes, move the macro definitions
into the new header file imx8_hsio.h.
- i.MX8QXP only have PCIe Control B. Enable PORT B at default.
i.MX8QM needs to set CONFIG_IMX_PCIEB to enable PORT B.
- Disable the LTSSM when link is down.Signed-off-by: Frank Li
Signed-off-by: Richard Zhu
Signed-off-by: Shenwei Wang
Signed-off-by: Ye Li
(cherry picked from commit 03141c2b955ce6034f06e701126aea1493dc2b4b)
(cherry picked from commit 99c90ff2de4849aafa0043932353e2c199d22e5f)
(cherry picked from commit ededb7dfeeb765bc64939dc8ba09c826568ff04e)
30 Mar, 2020
1 commit
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The pci-host-ecam-generic code assumes that the ECAM is the first PCI
bus in the system to be probed. Therefore, the system-wide bus number
allocated by U-Boot in sequence for it is going to be zero, which
corresponds to the memory-mapped config spaces found within it.Reuse the logic from other PCI bus drivers, and assume that U-Boot will
allocate bus numbers in sequence for all buses within the current ECAM.
So the base number of the bus needs to be subtracted when indexing the
correct config space.Fixes: 3675cb044e68 ("PCI: Add driver for a 'pci-host-ecam-generic' host controller")
Signed-off-by: Vladimir Oltean
Reviewed-by: Alex Marginean
Signed-off-by: Priyanka Jain
06 Feb, 2020
4 commits
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At present dm/device.h includes the linux-compatible features. This
requires including linux/compat.h which in turn includes a lot of headers.
One of these is malloc.h which we thus end up including in every file in
U-Boot. Apart from the inefficiency of this, it is problematic for sandbox
which needs to use the system malloc() in some files.Move the compatibility features into a separate header file.
Signed-off-by: Simon Glass
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At present devres.h is included in all files that include dm.h but few
make use of it. Also this pulls in linux/compat which adds several more
headers. Drop the automatic inclusion and require files to include devres
themselves. This provides a good indication of which files use devres.Signed-off-by: Simon Glass
Reviewed-by: Anatolij Gustschin -
Tidy up a few places where const * should be used.
Signed-off-by: Simon Glass
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At present this method uses a non-const udevice pointer, but the call
should not modify the device. Use a const pointer.Signed-off-by: Simon Glass
24 Jan, 2020
5 commits
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lx2160a rev1 requires layerscape_gen4 device tree fixup and
lx2160a rev2 requires layerscape device tree fixup.
Add device tree fixup for lx2160a based on SoC and Version.Signed-off-by: Wasim Khan
Reviewed-by: Priyanka Jain -
Move streamId allocation to layerscape common device tree fixup.
Calculate streamId based on SoC variant.Signed-off-by: Wasim Khan
Reviewed-by: Priyanka Jain -
Add Common device tree fixup for NXP SoCs. Based on
SoC and revision call pcie_layerscape or pcie_layerscape_gen4
fixup.Signed-off-by: Wasim Khan
Reviewed-by: Priyanka Jain -
There is not any difference for disabling BARs in RC mode
between PCIe controllers with and without SRIOV.Fixes: 80afc63fc342 ("pci: layerscape: add pci driver based on DM")
Signed-off-by: Hou Zhiqiang
Reviewed-by: Priyanka Jain -
The software will still get non-zero Expansion ROM BAR size
even when the BAR_EN bit is cleared. The BAR_EN bit of
register EXP_ROM_BAR_MASK_RC is not working as expected,
so this patch changes to mask all the bits.Fixes: 80afc63fc342 ("pci: layerscape: add pci driver based on DM")
Signed-off-by: Hou Zhiqiang
Reviewed-by: Priyanka Jain
18 Jan, 2020
1 commit
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This is an init-related function so belongs in that file. Move it.
Signed-off-by: Simon Glass
08 Jan, 2020
1 commit
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It is not possible to access a device on a PCI bus that has not yet been
probed, since the bus number is not known. Add a warning to catch this
error.Signed-off-by: Simon Glass
07 Jan, 2020
2 commits
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New for 2020.04
---------------- New boards
Embedded Artists COM board
Xea Board
- Switch to DM:
Aristainetos boards
Toradex colibri (DM_ETH)
iCubox
GE bx50v3
mx7dsabre (DM_ETH)
cx9020
- New features:
Bootaux with elf files
Default SYS_THUMB_BUILD for i.MX6/7
- Fixes:
DHCOM i.MX6 PDK
Engicam
i.MX8M tools (imx8m_image)Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/633679664
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The driver works fine with iMX6SX, add the missing compatible string.
Signed-off-by: Marek Vasut
Cc: Bin Meng
Cc: Fabio Estevam
Cc: Stefano Babic
02 Jan, 2020
2 commits
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The ep node device tree name is governed by these bindings:
https://github.com/torvalds/linux/blob/master/Documentation/
devicetree/bindings/pci/layerscape-pci.txt#L24As per above the ep compatible node contains platform name.
Therefore, define the ep node compatible as CONFIG to find the
pcie ep node in device tree during device tree fixup.Signed-off-by: Pankaj Bansal
Signed-off-by: Priyanka Jain -
move the PCIE related config from arch Kconfig to PCI Kconfig.
As the PCI_LAYERSCAPE driver is being used in platform other than
fsl-layerscape platforms like ls102xa.Signed-off-by: Pankaj Bansal
Signed-off-by: Priyanka Jain
26 Dec, 2019
5 commits
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Add FSL_PEX_STREAM_ID_END and remove FSL_PEX_STREAM_ID_NUM
for lx2160a.Signed-off-by: Wasim Khan
Reviewed-by: Priyanka Jain -
Update API names for layerscape gen4 fixup.
Suffix layerscape_gen4 fixup API names with _ls_gen4.
This is required to organize device tree fixup in common, layerscape
and layerscape_gen4 specific code.Signed-off-by: Wasim Khan
Reviewed-by: Priyanka Jain -
Suffix layerscape fixup API names with _ls.
This is required to organize device tree fixup in common,
layerscape and layerscape_gen4 specific code.Signed-off-by: Wasim Khan
Reviewed-by: Priyanka Jain -
Add stream_id_cur field to ls_pcie structure and initialize
it with 0 for all pcie controllers. This field will be used
for streamId calculation.Signed-off-by: Wasim Khan
Reviewed-by: Priyanka Jain -
lx2160a rev1 uses pcie_layerscape_gen4 driver and lx2160a rev2 uses
pcie_layerscape driver.
Enable pcie_layerscape code for CONFIG_PCIE_LAYERSCAPE_GEN4.
Based on SoC and revision pcie controller probe will be invoked.Signed-off-by: Wasim Khan
Signed-off-by: Priyanka Jain
15 Dec, 2019
3 commits
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Early in boot it is necessary to decode the PCI device/function values for
particular peripherals in the device tree or of-platdata. This is needed
in TPL where CONFIG_PCI is not defined.To handle this, move pci_get_devfn() into a file that is built even when
CONFIG_PCI is not defined.Also add a function for use by of-platdata, to convert a reg property to
a pci_dev_t.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
At present PCI auto-configuration happens in U-Boot both before and after
relocation. This is a waste of time and may mess up static addresses used
in board_init_f(). Adjust the code to supporting doing auto-configuration
once, after relocation, under control of a device-tree property.This is needed for Apollo Lake for debugging the silicon-init code. Once
the UART is moved to a different MMIO address the debug UART does not work
and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass
is included in SPL/TPL without any control for boards. Some boards may
want to disable this to reduce code size where GPIOs are not needed in
SPL or TPL.Add a new Kconfig option to permit this. Default it to 'y' so that
existing boards work correctly.Change existing uses of CONFIG_DM_GPIO to CONFIG_IS_ENABLED(DM_GPIO) to
preserve the current behaviour. Also update the 74x164 GPIO driver since
it cannot build with SPL.This allows us to remove the hacks in config_uncmd_spl.h and
Makefile.uncmd_spl (eventually those files should be removed).Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
05 Dec, 2019
1 commit
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PCI devices may be disabled in the device tree. Devices which are probed
by the device tree handle the "status" property and are skipped if
disabled. Devices which are probed by the PCI enumeration don't check
that property. Fix it.Signed-off-by: Michael Walle
Reviewed-by: Alex Marginean
Tested-by: Alex Marginean
Reviewed-by: Bin Meng
03 Dec, 2019
2 commits
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The content of pci_rom.c is only used in a few cases. Only build and
link in these cases to avoid a global variable as gcc doesn't always
discard those when they are unused.Signed-off-by: Tom Rini
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This function can be dropped when all boards use driver model for PCI. For
now, move it into init.h with a comment.Signed-off-by: Simon Glass
Reviewed-by: Tom Rini
12 Nov, 2019
1 commit
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- Rename CONFIG_SECURE_BOOT to CONFIG_NXP_ESBC.
- Few bug fixes and updates related to SPI, hwconfig, ethernet,
fsl-layerscape, pci, icid, PSCI
08 Nov, 2019
2 commits
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In ls_pcie_ep_enable_cfg(), as part of EP setup,config ready bit
of pci controller is set, so that RC can read the config space of EP.While setting the config ready bit, LTSSM_EN bit in same register was
also inadvertently getting cleared. This restarts the link training
between RC and EP.Update code to just set the desired CFG_READY bit (bit 0),
while leaving the other bits unchanged.Signed-off-by: Pankaj Bansal
Reviewed-by: Hou Zhiqiang
Signed-off-by: Priyanka Jain -
This adds platform code and the device tree for the Phytium Durian Board.
The initial support comprises the UART and the PCIE.Cc: Bin Meng
Cc: Kever Yang
Cc: Tom Rini
Cc: Heinrich SchuchardtSigned-off-by: Steven Hao
06 Nov, 2019
1 commit
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add DM based PCI Configuration space access support for
MPC85xx PCI Bridge. This driver is based on
arch/powerpc/cpu/mpc85xx/pci.cIn the old driver there is a fix for a hw issue on the
TARGET_MPC8555CDS and TARGET_MPC8541CDS boards. As I
have no such hardware I did not port this part.Signed-off-by: Heiko Schocher
Reviewed-by: Priyanka Jain
12 Oct, 2019
1 commit
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- Remember the device being emulated for Sandbox PCI
- Update Kconfig options for FSP 1.0
- Drop RESET_BASE and RESET_SEG_SIZE that are no longer used
11 Oct, 2019
2 commits
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This adds PCIe controller support for MT7623.
This is adapted from the Linux version.Tested-by: Frank Wunderlich
Signed-off-by: Ryder Lee
Signed-off-by: Frank Wunderlich -
Add a field to the PCI emulator per-device data which records which device
is being emulated. This is useful when the emulator needs to check the
device for something.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
Tested-by: Bin Meng
[bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly]
Signed-off-by: Bin Meng
08 Oct, 2019
1 commit
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The code in swapcase can be used by other sandbox drivers. Move it into a
common place to allow this.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
Tested-by: Bin Meng
[bmeng: remove inclusion of in pci_sandbox.c]
Signed-off-by: Bin Meng