11 May, 2019
1 commit
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Add default fitImage file bundling FPGA bitstreams for Arria10.
Signed-off-by: Tien Fong Chee
10 Mar, 2019
1 commit
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The Kconfig checked for SoCFPGA Arria10 as a platform, instead of
checking for specific board configuration, which works with one
single platform in tree, but not with multiple. Fix it.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Simon Goldschmidt
Cc: Tien Fong Chee
12 Jul, 2018
1 commit
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Add socdk board support for Stratix SoC
Signed-off-by: Chin Liang See
Signed-off-by: Ley Foon Tan
07 May, 2018
1 commit
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When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.Signed-off-by: Tom Rini
06 Nov, 2017
1 commit
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As part of my usual round of build testing, output about missing
MAINTAINERS information was not logged, and thus often overlooked.
Correct that mistake by ensuring that I log the output of
genboardscfg.py every time. As part of that, address a number of
missing MAINTAINERS entires. In the case of a missing file, I have put
the original submitter down. In the rest of the cases I have added the
config (and sometimes relevant header file) to the existing set of file
globs.Signed-off-by: Tom Rini
18 May, 2017
1 commit
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Add support for the Arria10 SoCDK.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
06 Dec, 2016
1 commit
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With the acquisition of Altera by Intel, my Altera email may be going
away soon. Update the contact to a more reliable address.Signed-off-by: Dinh Nguyen
27 Oct, 2016
1 commit
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Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stable LPDDR2 operation. Since the board is
using DDR3, the handoff is set to default value 0.Signed-off-by: Chin Liang See
Cc: Marek Vasut
Cc: Dinh Nguyen
11 May, 2016
1 commit
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Update the pinmux and pll configuration for the Cyclone5 RevE or later devkit.
Signed-off-by: Dinh Nguyen
23 Dec, 2015
4 commits
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Updated pinmux group GENERALIO[15-16] for i2c.
Signed-off-by: Chin Liang See
Cc: Dinh Nguyen
Cc: Dinh Nguyen
Cc: Pavel Machek
Cc: Marek Vasut
Cc: Stefan Roese
Cc: shengjiangwu -
Updated pinmux group EMACIO[1-8] and EMACIO[10-13] for USB.
Signed-off-by: shengjiangwu
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Dinh Nguyen
Cc: Pavel Machek
Cc: Marek Vasut
Cc: Stefan Roese -
Updated pinmux group MIXED1IO[15-20] for QSPI.
Updated QSPI clock.Signed-off-by: shengjiangwu
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Dinh Nguyen
Cc: Pavel Machek
Cc: Marek Vasut
Cc: Stefan Roese -
Updated pinmux group MIXED1IO[0-13] for RGMII1.
Updated EMAC1 clock.Signed-off-by: shengjiangwu
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Dinh Nguyen
Cc: Pavel Machek
Cc: Marek Vasut
Cc: Stefan Roese
20 Dec, 2015
5 commits
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Drop all the common board code, since it is not completely useless.
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen -
This patch adds the necessary OF alias for the UDC node, which let's
the code locate the DWC2 UDC base address in OF instead of hard-coding
it into the U-Boot binary. The code is adjusted to use the address from
OF instead of the hard-coded one. Finally, the hard-coded address is
removed and USB DM support is enabled.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Lukasz Majewski
Cc: Lukasz Majewski -
This patch adds the necessary OF alias for the UDC node, which let's
the code locate the DWC2 UDC base address in OF instead of hard-coding
it into the U-Boot binary. The code is adjusted to use the address from
OF instead of the hard-coded one. Finally, the hard-coded address is
removed and USB DM support is enabled.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Lukasz Majewski
Cc: Lukasz Majewski -
The Micrel PHY configuration is now done from OF, so hard-coding
the configuration into the board file is no longer necessary.Signed-off-by: Marek Vasut
Cc: Joe Hershberger
Cc: Chin Liang See
Cc: Dinh Nguyen -
The Micrel PHY configuration is now done from OF, so hard-coding
the configuration into the board file is no longer necessary.Signed-off-by: Marek Vasut
Cc: Joe Hershberger
Cc: Chin Liang See
Cc: Dinh Nguyen
18 Dec, 2015
3 commits
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The driver is actually for the Designware DWC2 controller.
This patch renames the global s3c_udc.h header to dwc2_udc.h.The rename is done automatically:
$ sed -i "s/s3c_udc\.h/dwc2_udc.h/g" \
`git grep "s3c_udc\.h" | cut -d : -f 1`Signed-off-by: Marek Vasut
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The driver is actually for the Designware DWC2 controller.
This patch is the second and final to rename global symbol,
the s3c_udc_probe() function.The rename is done automatically:
$ sed -i "s/s3c_udc_probe/dwc2_udc_probe/g" \
`git grep s3c_udc_probe | cut -d : -f 1`Signed-off-by: Marek Vasut
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The driver is actually for the Designware DWC2 controller.
This patch is the first to rename global symbol, the struct
s3c_plat_otg_data.The rename is done automatically:
$ sed -i "s/s3c_plat_otg_data/dwc2_plat_otg_data/g" \
`git grep s3c_plat_otg_data | cut -d : -f 1`Signed-off-by: Marek Vasut
12 Nov, 2015
1 commit
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Add 3c120 and 10m50 devboards MAINTAINERS
Signed-off-by: Thomas Chou
Acked-by: Marek Vasut
23 Oct, 2015
5 commits
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As we use device tree to control u-boot now, the generic
board can be removed.Signed-off-by: Thomas Chou
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Zap initdram(), as it is not used.
Signed-off-by: Thomas Chou
Acked-by: Marek Vasut -
Convert altera sysid to driver model with misc uclass.
Signed-off-by: Thomas Chou
Acked-by: Chin Liang See
Reviewed-by: Simon Glass -
Convert altera_pio to driver model.
Signed-off-by: Thomas Chou
Acked-by: Chin Liang See
Reviewed-by: Simon Glass -
As altera_pio_init() uses BSS, it should be moved to
board_early_init_r().Signed-off-by: Thomas Chou
Acked-by: Marek Vasut
23 Sep, 2015
1 commit
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commit "arm: socfpga: rename socfpga_cyclone5 and socfpga_arria5 config files"
renames the configs files, so we should update the MAINTAINERS' entry. At
the same time, update the email for Dinh Nguyen.Signed-off-by: Dinh Nguyen
23 Aug, 2015
8 commits
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Pull out the ArriaV SoCDK clock config from ancient Altera U-Boot
"rel_socfpga_v2013.01.01_15.05.01_pr" and implant those values into
mainline to get a booting ArriaV SoCDK.Signed-off-by: Marek Vasut
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Repair the maintainer entries so they match the current state of code.
Signed-off-by: Marek Vasut
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Now that we're actually converting the QTS-generated header files,
we can even adjust their data types. A good candidate for this is
the pinmux table, where each entry can have value in the range of
0..3, but each element is declared as unsigned long. By changing
the type to u8, we can save over 600 Bytes from the SPL, so do it.
This patch also constifies the array.Signed-off-by: Marek Vasut
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Signed-off-by: Marek Vasut
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Just remove the ArriaV specific parts from the CycloneV SoCDK board
and they are no longer needed now.Signed-off-by: Marek Vasut
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Just remove the CycloneV specific parts from the ArriaV SoCDK board
and they are no longer needed now.Signed-off-by: Marek Vasut
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The board/altera/socfpga directory is not a generic SoCFPGA machine
anymore, but instead it represents the Altera SoCDK board. To make
matters more complicated, it represents both CycloneV and ArriaV
variant.On the other hand, nowadays, the content of this board directory is
mostly comprised of QTS-generated header files, while all the generic
code is in arch/arm/mach-socfpga already.Thus, this patch splits the board/altera/socfpga into a separate
board directory for ArriaV SoCDK and CycloneV SoCDK, so that each
can be populated with the correct QTS-generated header files for
that particular board.Signed-off-by: Marek Vasut
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Move the wrappers for QTS-generated files into platform directory
out of the board directory. The trick here is to add -I to CFLAGS
such that it points to the board directory in source tree and thus
the qts/ directory there is still reachable.Signed-off-by: Marek Vasut
08 Aug, 2015
4 commits
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Fix build error for socfpga_cyclone5_defconfig:
board/altera/socfpga/wrap_sdram_config.c:245:26: error: ‘RW_MGR_MEM_NUMBER_OF_RANKS’ undeclared here (not in a function)
make[2]: *** [spl/board/altera/socfpga/wrap_sdram_config.o] Error 1Signed-off-by: Dinh Nguyen
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Introduce structure socfpga_sdram_misc_config to wrap the remaining
misc configuration values in board file. Again, introduce a function,
socfpga_get_sdram_misc_config(), which returns this the structure. This
is almost the final step toward wrapping the nasty QTS generated macros
in board files and reducing the pollution of the namespace.Signed-off-by: Marek Vasut
Acked-by: Dinh Nguyen -
Introduce structure socfpga_sdram_io_config to wrap the IO configuration
values in board file. Introduce socfpga_get_sdram_io_config() function,
which returns this the structure. This is another step toward wrapping
the nasty QTS generated macros in board files and reducing the pollution
of the namespace.Signed-off-by: Marek Vasut
Acked-by: Dinh Nguyen -
Introduce structure socfpga_sdram_rw_mgr_config to wrap the RW manager
configuration values in board file. Introduce a complementary function,
socfpga_get_sdram_rwmgr_config(), which returns this the structure.
This is another step toward wrapping the nasty QTS generated macros
in board files and reducing the pollution of the namespace.Signed-off-by: Marek Vasut
Acked-by: Dinh Nguyen