06 Aug, 2015
17 commits
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This PMIC is used with SoCs which need a combination of BUCKs and LDOs. The
driver supports probing and basic register access. It supports the standard
device tree binding and supports driver model. A regulator driver can be
provided also.Signed-off-by: Simon Glass
Acked-by: Przemyslaw Marczak -
The TPS65090 has 7 FETs which are modelled as regulators. This allows them
to be controlled by drivers easier, accessed through the 'regulator' command
and used by other drivers.Signed-off-by: Simon Glass
Acked-by: Przemyslaw Marczak -
The existing TPS65090 driver does not support driver model. Add a new one
that does. This can be used as a base for a regulator driver also. It uses
the standard device tree binding.Signed-off-by: Simon Glass
Acked-by: Przemyslaw Marczak -
As a debugging aid, allow UART3 to be used as a debug UART in SPL. This
is a precursor to proper UART support, which requires a substantial
refactor.Signed-off-by: Simon Glass
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Add a debug UART implementation for this serial driver. It does not set up
pinmux automatically - this must be done before calling debug_uart_init().Signed-off-by: Simon Glass
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The debug UART code needs to perform the same init as the normal UART
driver. In preparation for this, move the init code into two functions, one
for the basic init and one for setting the baud rate. This will make adding
debug UART support easier.Signed-off-by: Simon Glass
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Add a driver to support the special LDO access used by spring. This is a
custom method in the cros_ec protocol - it does not use an I2C
pass-through.There are two implementation choices:
1. Write a special LDO driver which can talk across the EC. Duplicate all
the logic from TPS65090 for retrying when the LDO fails to come up.2. Write a special I2C bus driver which pretends to be a TPS65090 and
transfers reads and writes using the LDO message.Either is distasteful. The latter method is chosen since it results in less
code duplication and a fairly simple (30-line) implementation of the core
logic.The crosec 'ldo' subcommand could be removed (since i2c md/mw will work
instead) but is retained as a convenience.Signed-off-by: Simon Glass
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The Chrome OS EC supports tunnelling through to an I2C bus on the EC. This
currently uses a copy of the I2C command code and a special 'crosec'
sub-command.With driver model we can define an I2C bus which tunnels through to the EC,
and use the normal 'i2c' command to access it. This simplifies the code and
removes some duplication.Add an I2C driver which tunnels through to the EC. Adjust the EC code to
support binding child devices so that it can be set up. Adjust the existing
I2C xfer function to fit driver model better.For now the old code remains to allow things to still work. It will be
removed in a later patch once the new flow is fully enabled.Signed-off-by: Simon Glass
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The existing driver model implementation uses the old non-driver-model code
to operate, but has become impossibly tangled as a result. The actual
algorithm is quite simple.Also the normal-speed and high-speed buses are quite different and it
doesn't seem that useful to put them in the same driver.Finally, there is a bug which breaks communication with the Maxim sound
codec and may cause problems with other device.Rewrite the driver model code for normal-speed operation so that it is
easier to understand, and fix the bug. Add a TODO to split the drivers.Signed-off-by: Simon Glass
Reviewed-by: Heiko Schocher -
This function should not use mixed case, and it is simpler to use
clrbits_le32() when clearing bits. Fix it.Signed-off-by: Simon Glass
Acked-by: Heiko Schocher -
While I2C supports multi-master buses this is difficult to get right.
The implementation on the master side in software is quite complex.
Clock-stretching and the arbitrary time that an I2C transaction can take
make it difficult to share the bus fairly in the face of high traffic.
When one or more masters can be reset independently part-way through a
transaction it is hard to know the state of the bus.This driver provides a scheme based on two 'claim' GPIOs, one driven by the
AP (Application Processor, meaning the main CPU) and one driven by the EC
(Embedded Controller, a small CPU aimed at handling system tasks). With
these they can communicate and reliably share the bus. This scheme has
minimal overhead and involves very little code. It is used on snow to
permit the EC and the AP to share access to the main system PMIC and
battery. The scheme can survive reboots by either side without difficulty.
This scheme has been tested in the field with millions of devices.Since U-Boot runs on the AP, the terminology used is 'our' claim GPIO,
meaning the AP's, and 'their' claim GPIO, meaning the EC's. This terminology
is used by the device tree bindings in Linux also.Signed-off-by: Simon Glass
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Add a new I2C_MUX uclass. Devices in this class can multiplex between
several I2C buses, selecting them one at a time for use by the system.
The multiplexing mechanism is left to the driver to decide - it may be
controlled by GPIOs, for example.The uclass supports only two methods: select() and deselect().
The current mux state is expected to be stored in the mux itself since
it is the only thing that knows how to make things work. The mux can
record the current state and then avoid switching unless it is necessary.
So select() can be skipped if the mux is already in the correct state.
Also deselect() can be made a nop if required.Signed-off-by: Simon Glass
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Sometimes it is useful to be able to transfer a raw I2C message. This
happens when the chip address needs to be set manually, or when the data to
be sent/received is in another buffer.Add a function to provide access to this.
Signed-off-by: Simon Glass
Acked-by: Heiko Schocher -
Add a way to dump the contents of an I2C message for debugging purposes.
Signed-off-by: Simon Glass
Acked-by: Heiko Schocher -
It is common for one node to reference another via a phandle. Add support
for obtaining an attached device by this method. As an example, a node may
have a 'power-supply' property which references a regulator, allowing the
driver to turn on its power.Signed-off-by: Simon Glass
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Remove DEBUG in drivers/pci/pci_compat.c.
Signed-off-by: Bin Meng
Acked-by: Simon Glass
05 Aug, 2015
21 commits
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This patch fixes operation of our on-board AX88772B chip without EEPROM
but with a ethaddr coming from the regular U-Boot environment. This is
a forward port of some remaining parts initially implemented by
Antmicro.Signed-off-by: Marcel Ziswiler
Acked-by: Marek Vasut -
usb_stor_reset is only defined when USB storage support is enabled, thus the
function is not declared when such support is missing.Signed-off-by: Paul Kocialkowski
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Currently, the second use of a gadget will fail, while the first one works.
Forcing the EP0 at every enable fix this issue.
Signed-off-by: Maxime Ripard
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Now that the musb-new driver has a Kconfig, we can move Kconfig options to
enable controllers to it, so that it's easier in e.g. menuconfig.In addition, this allows declaring support for USB_MUSB_HOST/GADGET in
defconfigs instead of the USB_MUSB_SUNXI controller, that will get selected
automatically when needed.Signed-off-by: Paul Kocialkowski
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Having MUSB_HOST and MUSB_GADGET in Kconfig allows more flexibility with regard
to what Kconfig options to enable, such as USB_STORAGE or USB_KEYBOARD.Signed-off-by: Paul Kocialkowski
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USB-related options are usually prefixed with CONFIG_USB and platform-specific
adaptation for the MUSB controller already have a CONFIG_USB_MUSB prefix, so
this switches all MUSB-related options to a CONFIG_USB_MUSB prefix, for
consistency.Signed-off-by: Paul Kocialkowski
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There is no particular reason why the USB Kconfig option should be specific to
host mode. In prevision of adding MUSB host and gadget to Kconfig, this moves
the title and help message of the USB Kconfig option to a more generic format.Adding comments to the usb Kconfig allows for a better separation and more
readability in generated configs and in menuconfig.Signed-off-by: Paul Kocialkowski
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The USB_ARCH_HAS_HCD currently serves no purpose and adds some confusion to the
required Kconfig options that are required to have USB support.Dropping it makes things easier and doesn't break anything, since it was unused
anyways.Signed-off-by: Paul Kocialkowski
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This patch makes the dwc2 controller like ehci / ohci / xhci controllers
by calling the board_usb_init() function from usb_lowlevel_init.This can then be implemented by specific platforms to initialise
their USB hardware (phys / clocks etc).Signed-off-by: Peter Griffin
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We cannot use this driver when running from EFI as we have no direct hardware
access. In fact coreboot uses a different driver which uses tables provided
by coreboot. So far it does not seem possible to use a normal video driver
when booting from EFI.Signed-off-by: Simon Glass
Acked-by: Anatolij Gustschin
Reviewed-by: Bin Meng -
Add a serial driver which makes use of EFI's console in/out service.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
Tested on Intel Crown Bay and QEMU
Tested-by: Bin Meng -
Move this config option to Kconfig and tidy up.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
At present the PCI output displays 'Mem' when it allocates memory for a PCI
device, whether it is prefetchable or not. There is a distinction since the
memory comes from separate pools. Use 'Prf' instead of 'Mem' when allocating
prefetchable memory.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
Rather than using 0xff in the code, add a constant.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
This option is not used by any board but appears to still be useful, at least
for testing. With recent commits it does not build, so fix it.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
This file does not need its own way of doing debug(). Clean it up to use the
new way.Signed-off-by: Simon Glass
Acked-by: Pavel Machek
Reviewed-by: Bin Meng -
Some files use global_data but don't declare it. Fix this.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
In a final attempt to find a console UART this function uses the first
first available serial device. However the check for a valid device is
inverted.This code is only executed when there is in fact no serial UART, but at
present it can fail to reach the panic_str() call in this case, and start
trying to use a non-existent UART.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
This function needs to check the list has entries before traversing it.
Fix this bug.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
We should not set up kernel screen_info when the vesa parameters are
insane, otherwise kernel will panic.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
On some platforms pci devices behind bridge need to be probed (eg:
a pci uart on recent x86 chipset) before relocation. Remove such
limitation so that dm pci can be used before relocation.Signed-off-by: Bin Meng
Acked-by: Simon Glass
04 Aug, 2015
2 commits
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By default the bstopre value has been set to 0x100, used to be 1/4
value of refint. Modern DDR has increased the refresh time. Adjust
to 1/4 of refresh interval dynamically. Individual board can still
override this value in board ddr file, or to use auto-precharge.Signed-off-by: York Sun
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Signed-off-by: Horia Geantă
Acked-by: Ruchika Gupta
Reviewed-by: York Sun
