24 Sep, 2013

3 commits


21 Sep, 2013

2 commits


20 Sep, 2013

20 commits


18 Sep, 2013

8 commits

  • When CONFIG_MMC_SPI is not enabled, the MMC_MODE_SPI capability can
    never be set. However there is code in mmc.c which uses the
    mmc_host_is_spi macro to check that capability & act accordingly. If we
    expand that macro to 0 when CONFIG_MMC_SPI is not set (since it will
    always be 0 at runtime anyway) then the compiler can optimize away the
    SPI-specific code paths in mmc.c.

    Signed-off-by: Paul Burton

    Paul Burton
     
  • If we don't have CONFIG_SPL_LIBCOMMON_SUPPORT defined then stdio
    & *printf functions are unavailable & calling them will cause a link
    failure.

    Signed-off-by: Paul Burton

    Paul Burton
     
  • If we don't have CONFIG_SPL_LIBCOMMON_SUPPORT defined then stdio
    functions are unavailable & calling them will cause a link failure.

    Signed-off-by: Paul Burton

    Paul Burton
     
  • ARM is the only architecture which includes this header and nothing in
    spl_mmc.c makes use of it. Remove the include.

    Signed-off-by: Paul Burton

    Paul Burton
     
  • Enable 8-bit host capability for HSMMC2 and/or HSMMC3. CONFIG_HSMMC2_8BIT
    (for OMAP4/5/DRA7xx) and/or CONFIG_HSMMC3_8BIT (for DRA7xx only) must be
    defined in the board header if an 8-bit eMMC device is connected to the
    corresponding port.

    Fix the "No status update" error that appeared for eMMC devices by
    inserting a 20 us delay between writing arguments and command. This
    solution has been proposed by Michael Cashwell .

    A minor cosmetic fix in a comment as well.

    Signed-off-by: Lubomir Popov

    Lubomir Popov
     
  • "mmc_send_cmd: timeout: No status update" error sometimes happens in
    omap_hsmmc driver func mmc_send_cmd() when the MMC controller card
    identification and selection sequence is executed for eMMC on OMAP4
    boards.

    It happens due to incorrect execution of CMD line reset procedure
    for OMAP4. Because CMD(DAT) lines reset procedures are slightly
    different for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).

    According to OMAP3 TRM:
    Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until
    it returns to 0x0.

    According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
    procedure steps must be as follows:
    1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
    MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
    2. Poll the SRC(SRD) bit until it is set to 0x1.
    3. Wait until the SRC(SRD) bit returns to 0x0
    (reset procedure is completed).

    Unfortunately, at present omap_hsmmc driver has support only for
    OMAP3. And as result step #2 is missing for OMAP4(AM335x,OMAP5,DRA7xx).
    This sometimes leads to the fact that the waiting loop which is
    required in step #3 does not executed, because SRC bit does not set
    yet (at the moment of checking a condition of a loop execution).
    And as a result this can cause to timeout error when sending a
    next command.

    In the particular case (working with eMMC witch do not respond to
    some SD specific command) due to incorrect reset sequence after
    command SD_CMD_SEND_IF_COND which finished with CTO flag within
    64 clock cycles, the next command MMC_CMD_APP_CMD leads to a
    timeout error within 1s.

    So, extend CMD(DATA) lines reset procedure in func
    mmc_reset_controller_fsm() by adding the missing step #2 for
    OMAP4+/AM335x boards.

    Signed-off-by: Oleksandr Tyshchenko
    Acked-by: Pantelis Antoniou

    Oleksandr Tyshchenko
     
  • Do not call a memset for unused variable backup every time.
    Remove unused variable from function.

    Signed-off-by: Oleksandr Tyshchenko
    Acked-by: Pantelis Antoniou

    Oleksandr Tyshchenko
     
  • Samsung SoC is supported the WIDE8, even if Controller version is v2.0.
    So add the SDHCI_QUIRK_USE_WIDE8 for Samsung-SoC.

    Signed-off-by: Jaehoon Chung
    Signed-off-by: Kyungmin Park
    Signed-off-by: Pantelis Antoniou

    Jaehoon Chung
     

17 Sep, 2013

2 commits


14 Sep, 2013

1 commit


12 Sep, 2013

3 commits


11 Sep, 2013

1 commit