17 Mar, 2016
34 commits
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It is useful to automate the process of converting code from coreboot a
little. Add a sed script which performs some common transformations.Signed-off-by: Simon Glass
Acked-by: Bin Meng -
The Intel GPIO driver can set up the GPIO pin mapping when the first GPIO
is probed. However, it assumes that the first GPIO to be probed is in the
first GPIO bank. If this is not the case then the init will write to the
wrong registers.Fix this. Also add a note that this code is deprecated. We should move to
using device tree instead.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
At present the board ID GPIOs are hard-coded. Move them to the device tree
so that we can use general SDRAM init code.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
The SDRAM SPD (Serial Presence Detect) information should be contained
with the SDRAM controller. This makes it easier for the controller to access
it and removes the need for a separate compatible string.As a first step, move the information.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
In order to use GPIO phandles we need to add some GPIO properties as
specified by the GPIO bindings. Add these for link.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
Many of the model-specific indexes are common to several Intel CPUs. Add
some more common ones, and remove them from the ivybridge-specific header
file.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
This does not need to be modified at run-time, so make it const.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
Output the pointer returned by each call to malloc(). This can be useful
when debugging memory problems.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
Two comments are missing a parameter and there is an extra blank line. Also
two of the region access macros are misnamed. Correct these problems.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
It is common to read a config register value, clear and set some bits, then
write back the updated value. Add functions to do this in one step, for
convenience.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
Some functions do not change the struct gpio_desc parameter. Update these to
use const so this is clear.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
We can use GPIOs as binary digits for reading 'strapping' values. Each GPIO
is assigned a single bit and can be set high or low on the circuit board. We
already have a legacy function for reading these values. Add one that
supports driver model.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
Some CPUs use microcode and each core can have a different version of
microcode loaded. Also some CPUs support the concept of an integer ID used
for identification purposes. Add support for these in the CPU uclass.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
At present simple-panel requires regulator support and will not build
without it. But some panels do not have a power supply, or at least not one
that can be controlled. Update the implementation to cope with this.Signed-off-by: Simon Glass
Acked-by: Anatolij Gustschin -
Boting SeaBIOS is done via U-Boot's bootelf command. Document this.
Signed-off-by: Bin Meng
Reviewed-by: Simon Glass -
Now that ACPI is supported on QEMU, enable it.
Signed-off-by: Bin Meng
Reviewed-by: Simon Glass -
SeaBIOS is an open source implementation of a 16-bit x86 BIOS.
It can run in an emulator or natively on x86 hardware with the
use of coreboot. With SeaBIOS's help, we can boot some OSes
that require 16-bit BIOS services like Windows/DOS.As U-Boot, we have to manually create a table where SeaBIOS gets
system information (eg: E820) from. The table unfortunately has
to follow the coreboot table format as SeaBIOS currently supports
booting as a coreboot payload.Signed-off-by: Bin Meng
Reviewed-by: Simon Glass -
To prepare generating coreboot table from U-Boot, implement functions
to handle the writing.Signed-off-by: Bin Meng
Reviewed-by: Simon Glass -
For those secondary bootloaders like SeaBIOS who want to live in
the F segment, which conflicts the configuration table address,
now we allow write_tables() to write the configuration tables in
high area (malloc'ed memory).Signed-off-by: Bin Meng
Reviewed-by: Simon Glass -
Given all table write routines have the same signature, we can
simplify the codes by using a function table.Signed-off-by: Bin Meng
Reviewed-by: Simon Glass -
Change the parameter and return value of write_acpi_tables() to u32
to conform with other table write routines.Signed-off-by: Bin Meng
Reviewed-by: Simon Glass -
Define ROM_TABLE_ALIGN instead of using 1024 directly.
Signed-off-by: Bin Meng
Reviewed-by: Simon Glass -
Add a new variable rom_table_start and pass it to ROM table write
routines. This reads better than previous single rom_table_end.Signed-off-by: Bin Meng
Reviewed-by: Simon Glass -
Clean up this file a little bit:
- Remove inclusion of
- Use tab in the macro definitionSigned-off-by: Bin Meng
Reviewed-by: Simon Glass -
coreboot_tables.h should not include sysinfo related stuff.
Move those to asm/arch-coreboot/sysinfo.h.Signed-off-by: Bin Meng
Reviewed-by: Simon Glass -
Move asm/arch-coreboot/tables.h to asm/coreboot_tables.h so that
coreboot table definitions can be used by other x86 builds.Signed-off-by: Bin Meng
Reviewed-by: Simon Glass -
Starting with 96e5b03 we use a linker list for partition table
information. However since we use this in SPL we need to make sure that
the SPL linker scripts include these as well. While doing this, it's
best to simply include all linker lists to future proof ourselves.Cc: Andreas Bießmann
Acked-by: Michal Simek
Reviewed-by: Simon Glass
Reported-by: Nishanth Menon
Tested-by: Nishanth Menon
Signed-off-by: Tom Rini -
When we switch to including all linker lists in SPL it is important to
not include commands as that may lead to link errors due to other things
we have already discarded. In this case as we don't have other common
code nor other Synology borads, move the cmd_syno.c file (which claims
to be ds414 specific anyways!) into the ds414 directory and only build
it for non-SPL builds.Signed-off-by: Tom Rini
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On OMAP4 platforms that also need to calculate their DDR settings we are
now getting very close to the linker limit size. Since OMAP44XX is only
seen with LPDDR2, remove some run time tests for LPDDR2 or DDR3 as we
will know that we don't have it for OMAP44XX.Cc: Nishanth Menon
Signed-off-by: Tom Rini -
When we switch to including all linker lists in SPL it is important
to not include commands as that may lead to link errors due to other
things we have already discarded. In this case change things so that we
only build the right objects for SPL or non-SPLCc: Albert ARIBAUD (3ADEV)
Signed-off-by: Tom Rini -
When we switch to including all linker lists in SPL it is important
to not include commands as that may lead to link errors due to other
things we have already discarded. In this case, the SCSI code needs a lot
of attention so for now just guard the command portions.Signed-off-by: Tom Rini
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When we switch to including all linker lists in SPL it is important
to not include commands as that may lead to link errors due to other
things we have already discarded. In this case simply move cmd_ddr3.o
over to the list with the rest.Cc: Vitaly Andrianov
Cc: Nishanth Menon
Cc: Lokesh Vutla
Signed-off-by: Tom Rini -
Now that we have a standard way to power off the hardware, switch to
using that rather than our own command.Cc: Vitaly Andrianov
Cc: Nishanth Menon
Cc: Lokesh Vutla
Signed-off-by: Tom Rini -
When we switch to including all linker lists in SPL it is important
to not include commands as that may lead to link errors due to other
things we have already discarded. In this case, we split the code for
supporting the monitor out from the code for loading it.Cc: Vitaly Andrianov
Cc: Nishanth Menon
Cc: Lokesh Vutla
Signed-off-by: Tom Rini
16 Mar, 2016
6 commits
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NFS loading works on DRA7 variants, remove the undefinition.
Signed-off-by: Andrew F. Davis
Reviewed-by: Tom Rini -
NFS loading is similar to net loading except initial files are loaded
over NFS instead of TFTP, this removes the need for multiple different
protocol servers running on the host and allows the use of a single
network file system containing boot related files in their usual
in-filesystem directory. Add defaults for this boot style here.Signed-off-by: Andrew F. Davis
Reviewed-by: Tom Rini -
Fix "warning: cast to pointer from integer of different size".
Signed-off-by: Masahiro Yamada
Reviewed-by: Tom Rini -
If EMIF is idle for certain amount of DDR cycles, EMIF will put the
DDR in self refresh mode to save power if EMIF_PWR_MGMT_CTRL register
is programmed. And also before entering suspend-resume ddr needs to
be put in self-refresh. Linux kernel does not program this register
before entering suspend and relies on u-boot setting.
So configuring it in u-boot.Signed-off-by: Nishanth Menon
Signed-off-by: Lokesh Vutla
Tested-by: Tom Rini
Reviewed-by: Tom Rini -
For k2l, k2e and k2hk, ubi is set to default boot in uboot
environment settings; while for k2g, mmc should be the
default boot. This patch is to set mmc as default for k2g-evmSigned-off-by: Yan Liu
Signed-off-by: Lokesh Vutla
Reviewed-by: Tom Rini -
This patch updates the env script to include a initramfs with firmware
loaded and provided to kernel through second argument of bootz command
during boot. Defined DEFAULT_FW_INITRAMFS_BOOT_ENV to have all of the
required env variables and use it in evm specific config file.The K2 linux drivers for PCIe and NetCP (1G, 10G) requires serdes
firmwares. These requires firmware to be available early through the boot
process in some cases to satisfy firmware requests from driver. Hence use
a small initramfs to provide the same and update boot env to accommodate
this in the boot flow. This method is used when rootfs is nfs and ubifs.
This fs contains just lib/firmware folder with all required firmware.When rootfs is on initramfs, then the filesystem has the firmware under
lib/firmware and this early initramfs is not required and is not used.Signed-off-by: Murali Karicheri
Signed-off-by: Lokesh Vutla
Reviewed-by: Tom Rini
