18 Nov, 2013
13 commits
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Signed-off-by: Masahiro Yamada
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CONFIG_IXP4XX_NPE is defined only for CPU ixp.
It is not necessary to filter by CPU ixp.Signed-off-by: Masahiro Yamada
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CONFIG_FMAN_ENET is defined only for CPU mpc85xx.
We do not need to filter by CPU mpc85xx.Signed-off-by: Masahiro Yamada
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Signed-off-by: Masahiro Yamada
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Signed-off-by: Masahiro Yamada
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We do not need to handle $(LIBBOARD) and $(LIBS) separately.
Signed-off-by: Masahiro Yamada
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Signed-off-by: Masahiro Yamada
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Signed-off-by: Masahiro Yamada
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Signed-off-by: Masahiro Yamada
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- Descend into drivers/fpga/ only when CONFIG_FPGA=y
- Descend into drivers/bios_emulator only when CONFIG_BIOSEMU=ySigned-off-by: Masahiro Yamada
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Signed-off-by: Masahiro Yamada
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The support for COBJS, COBJS-y, SOBJS, SOBJS-y, GLCOBJS, GLSOBJS
from scripts/Makefile.build.
Going forward we need to use Kbuild style consistently.Signed-off-by: Masahiro Yamada
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Board config.mk do not need to add -DCONFIG_SYS_TEXT_BASE
to CPPFLAGS because the top level config.mk does instead.Signed-off-by: Masahiro Yamada
16 Nov, 2013
6 commits
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Commit 309a292e deleted OXC board, but
missed to remove the standalone example specific to OXC board.eepro100_eeprom.c has been an orphan file for a long term.
Signed-off-by: Masahiro Yamada
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Commit 7e8c53d7 removed eNET board but missed to
add eNET to README.scrapyard.
This commit adds it for the record.Signed-off-by: Masahiro Yamada
Cc: Simon Glass
Cc: Graeme Russ
Acked-by: Simon Glass -
Signed-off-by: Masahiro Yamada
Cc: Thomas Chou -
Signed-off-by: Masahiro Yamada
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Since commit c2dd0d455 and 45bf05854 introduced
the new cache maintainance framework to ARM,
CONFIG_L2_OFF has not been used at all.Signed-off-by: Masahiro Yamada
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In 6789e84 we update u-boot-spl.lds for OMAP to ensure we include
adapter information, as we use i2c during SPL. However, the regex used
also means we included commands that may have been built. On omap5_uevm
this leads to a failure as we include the command from the do_tca642x
command, and fail to link. The fix is to restrict our regex to only the
i2c list parts.Signed-off-by: Tom Rini
15 Nov, 2013
1 commit
14 Nov, 2013
9 commits
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When indexing freqProcessor[] we use the first
value in the cpu's "reg" property, which on
new e6500 cores IDs the threads.
But freqProcessor[] should be indexed with a
core index so, when fixing "the clock-frequency"
cpu node property, access the freqProcessor[]
with the core index derived from the "reg' property.
If we don't do this, last half of the "cpu" nodes
will have broken "clock-frequency" values.Signed-off-by: Laurentiu Tudor
Cc: York Sun -
Update the code that builds the pci endpoint liodn
offset list so that it doesn't overlap with other
liodns and doesn't generate negative offsets like:fsl,liodn-offset-list = ;
The update consists in adding a parameter to the
function that builds the list to specify the base
liodn.
On PCI v2.4 use the old base = 256 and, on PCI 3.0
where some of the PCIE liodns are larger than 256,
use a base = 1024. The version check is based on
the PCI controller's version register.Signed-off-by: Laurentiu Tudor
Cc: Scott Wood
Cc: York Sun -
The liodn for the T4240's PCIE controller is no longer set
through a register in the guts register block but with one
in the PCIE register block itself.
Use the already existing SET_PCI_LIODN_BASE macro that puts
the liodn in the correct register.Signed-off-by: Laurentiu Tudor
Cc: Scott Wood
Cc: York Sun -
Define base addresse for both MPH(USB1) and DR(USB2) controllers
for MPC834x socsSigned-off-by: Ramneek Mehresh
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T1042RDB_PI is Freescale Reference Design Board supporting the T1042
QorIQ Power Architecture™ processor. T1042 is a reduced personality
of T1040 SoC without Integrated 8-port Gigabit. The board is designed
with low power features targeted for Printing Image Market.T1042RDB_PI is similar to T1040RDB board with few differences like
it has video interface, supports T1042 personalityT1042RDB_PI board Overview
-----------------------
- Four e5500 cores, each with a private 256 KB L2 cache
- 256 KB shared L3 CoreNet platform cache (CPC)
- Interconnect CoreNet platform
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
support
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
for the following functions:
- Packet parsing, classification, and distribution
- Queue management for scheduling, packet sequencing, and congestion
management
- Cryptography Acceleration
- RegEx Pattern Matching Acceleration
- IEEE Std 1588 support
- Hardware buffer management for buffer allocation and deallocation
- Ethernet interfaces
- Two on-board RGMII 10/100/1G ethernet ports.
- SERDES Connections, 8 lanes supporting:
— PCI
— SATA 2.0
- DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and
Interleaving
-IFC/Local Bus
- NAND flash: 1GB 8-bit NAND flash
- NOR: 128MB 16-bit NOR Flash
- Ethernet
- Two on-board RGMII 10/100/1G ethernet ports.
- PHY #0 remains powered up during deep-sleep
- CPLD
- Clocks
- System and DDR clock (SYSCLK, “DDRCLK”)
- SERDES clocks
- Video
- DIU supports video at up to 1280x1024x32bpp
- HDMI connector
- Power Supplies
- USB
- Supports two USB 2.0 ports with integrated PHYs
- Two type A ports with 5V@1.5A per port.
- SDHC
- SDHC/SDXC connector
- SPI
- On-board 64MB SPI flash
- I2C
- Device connected: EEPROM, thermal monitor, VID controller, RTC
- Other IO
- Two Serial ports
- ProfiBus port
- Four I2C portsSigned-off-by: Poonam Aggrwal
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Priyanka Jain -
T1040RDB is Freescale Reference Design Board supporting
the T1040 QorIQ Power Architecture™ processor.T1040RDB board Overview
-----------------------
- Four e5500 cores, each with a private 256 KB L2 cache
- 256 KB shared L3 CoreNet platform cache (CPC)
- Interconnect CoreNet platform
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
support
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
for the following functions:
- Packet parsing, classification, and distribution
- Queue management for scheduling, packet sequencing, and congestion
management
- Cryptography Acceleration
- RegEx Pattern Matching Acceleration
- IEEE Std 1588 support
- Hardware buffer management for buffer allocation and deallocation
- Ethernet interfaces
- Integrated 8-port Gigabit Ethernet switch
- Four 1 Gbps Ethernet controllers
- SERDES Connections, 8 lanes supporting:
- PCI
- SGMII
- QSGMII
- SATA 2.0
- DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and
Interleaving
-IFC/Local Bus
- NAND flash: 1GB 8-bit NAND flash
- NOR: 128MB 16-bit NOR Flash
- Ethernet
- Two on-board RGMII 10/100/1G ethernet ports.
- PHY #0 remains powered up during deep-sleep
- CPLD
- Clocks
- System and DDR clock (SYSCLK, “DDRCLK”)
- SERDES clocks
- Power Supplies
- USB
- Supports two USB 2.0 ports with integrated PHYs
- Two type A ports with 5V@1.5A per port.
- SDHC
- SDHC/SDXC connector
- SPI
- On-board 64MB SPI flash
- I2C
- Devices connected: EEPROM, thermal monitor, VID controller
- Other IO
- Two Serial ports
- ProfiBus portSigned-off-by: Poonam Aggrwal
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Priyanka Jain
[York Sun: fixed Makefile]
Acked-by: York Sun -
T1040 Soc has four personalities:
-T1040 (4 cores with L2 switch)
-T1042:Reduced personality of T1040 without L2 switch
-T1020:Reduced personality of T1040 with less cores(2 cores)
-T1022:Reduced personality of T1040 with 2 cores and without L2 switchUpdate defines in arch/powerpc header files, Makefiles and in
driver/net/fm/Makefile to support all T1040 personalitiesSigned-off-by: Poonam Aggrwal
Signed-off-by: Priyanka Jain
[York Sun: fixed Makefiles]
Acked-by: York Sun -
- Remove duplicate doc/README.p1010rdb
- Rename README to README.P1010RDB-PA
- Add new README.P1010RDB-PBP1010RDB-PB is a variation of previous P1010RDB-PA board.
Signed-off-by: Shengzhou Liu
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Use a default RCW of protocol 0x66.
A PBI configure file which uses CPC as 256KB SRAM. It can be used by
PBL tool on T1040 to build a pbl boot image.Signed-off-by: Prabhakar Kushwaha
13 Nov, 2013
8 commits
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This delay applies to any data transfer on I2C bus.
For example 1kB data read with per-byte access (which happens if
environment is stored in I2C EEPROM) takes more than 10 seconds.Moreover data bus driver has to care about bus state and data transfer,
but not about internal states of attached devices.Signed-off-by: Alexey Brodkin
Cc: Tom Rini
cc: Armando Visconti
Cc: Stefan Roese
Cc: Albert ARIBAUD
Cc: Heiko Schocher
Cc: Vipin KUMAR
Cc: Tom Rix
Cc: Mischa Jonker -
As it is stated in DesignWare I2C databook: writes to IC_TAR (0x4)
register succeed only when IC_ENABLE[0] is set to 0.Signed-off-by: Alexey Brodkin
Cc: Tom Rini
cc: Armando Visconti
Cc: Stefan Roese
Cc: Albert ARIBAUD
Cc: Heiko Schocher
Cc: Vipin KUMAR
Cc: Tom Rix
Cc: Mischa Jonker -
Data "offset" is not used directly in case of I2C EEPROM. Istead it is
split into "block number" and "offset within mentioned block". Which are
"addr[0]" and "addr[1]" respectively.Signed-off-by: Alexey Brodkin
Cc: Jean-Christophe PLAGNIOL-VILLARD
cc: Peter Tyser
Cc: Heiko Schocher
Cc: Wolfgang Denk
Cc: Stefan Roese
Cc: Mischa Jonker -
remove omap1510 i2c driver, as there is no board which uses it
Signed-off-by: Heiko Schocher
Cc: Tom Rini
Cc: Jian Zhang -
- add zync i2c driver to new multibus/multiadpater support
- adapted all config files, which uses this driverSigned-off-by: Heiko Schocher
Cc: Joe Hershberger
Cc: Michal Simek -
- add omap24xx driver to new multibus/multiadpater support
- adapted all config files, which uses this driverTested on the am335x based siemens boards rut, dxr2 and pxm2
posted here:
http://patchwork.ozlabs.org/patch/263211/Signed-off-by: Heiko Schocher
Tested-by: Tom Rini
Cc: Lars Poeschel
Cc: Steve Sakoman
Cc: Thomas Weber
Cc: Tom Rix
Cc: Grazvydas Ignotas
Cc: Enric Balletbo i Serra
Cc: Luca Ceresoli
Cc: Igor Grinberg
Cc: Ilya Yanok
Cc: Stefano Babic
Cc: Nishanth Menon
Cc: Pali Rohár
Cc: Peter Barada
Cc: Nagendra T S
Cc: Michael Jones
Cc: Raphael Assenat
Acked-by: Igor Grinberg
Acked-by: Stefano Babic -
The endless waiting for a bit to be set can cause a hang, add a timeout
so we prevent such situation. A testcase for such a hang is below. The
testcase assumes a device to be present at address 0x50 and a device to
NOT be present at address 0x42 . Also note that the "sleep 1" induced
delays are imperative for this bug to manifest .i2c read 0x42 0x0.2 0x10 0x42000000 ; sleep 1 ; \
i2c read 0x50 0x0.2 0x10 0x42000000 ; sleep 1 ; \
i2c read 0x42 0x0.2 0x10 0x42000000The expected result of the above command is:
Error reading the chip.
Error reading the chip.While without this patch, we observe a hang in the last read from 0x42
precisely when waiting for this bit to be set.Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: Heiko Schocher
Cc: Stefano Babic -
This updates to new I2C framwwork on sh_i2c.
And this also updates boards(kzm9g and ecovec) that using sh_i2c.Signed-off-by: Nobuhiro Iwamatsu
Signed-off-by: Nobuhiro Iwamatsu
12 Nov, 2013
3 commits
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Use scf0403 driver to add scf0403x LCD support for cm-t35 and cm-t3730
boards.Signed-off-by: Nikita Kiryanov
Acked-by: Igor Grinberg -
Add DSS_ONOFF to polarity defines
Cc: Tom Rini
Cc: Anatolij Gustschin
Cc: Igor Grinberg
Signed-off-by: Nikita Kiryanov
Acked-by: Igor Grinberg
Acked-by: Anatolij Gustschin -
Add SPI-based driver for DataImage SCF0403852GGU04 and SCF0403526GGU20
LCD panels.Cc: Tom Rini
Cc: Anatolij Gustschin
Cc: Igor Grinberg
Signed-off-by: Nikita Kiryanov
Acked-by: Anatolij Gustschin
Signed-off-by: Anatolij Gustschin
