14 Jul, 2009
32 commits
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Remove individual CPU specific DSPI driver.
Add required feature for the common DSPI driver in cpu_init and
in platform configuration file.Signed-off-by: TsiChung Liew
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Unify both MCF5227x and MCF5445x DSPI driver in CPU to
driver/spi folder for common use.Signed-off-by: TsiChung Liew
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Remove unused variables and printf type mismatch in
lib_m68k/board.cSigned-off-by: TsiChung Liew
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Increase the flash size from 8MB to 16MB
Signed-off-by: TsiChung Liew
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Signed-off-by: TsiChung Liew
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Update serial boot DRAM's Internal RAM, vector table and DRAM in
start.S, serial flash's read status command over SPI and NOR
flash.Signed-off-by: TsiChung Liew
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Update M52277EVB, M53017EVB and M54455EVB platform configuration
file to use flash buffer writeSigned-off-by: TsiChung Liew
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Signed-off-by: Wolfgang Denk
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Signed-off-by: Wolfgang Denk
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Signed-off-by: Wolfgang Denk
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Signed-off-by: Wolfgang Denk
Cc: Stefan Roese
Cc: Reinhard Arlt -
Remove dead code that was obviously a left-over from copy & paste.
Signed-off-by: Wolfgang Denk
Cc: Stefan Roese
Cc: Reinhard Arlt -
Needed for Rev. 2 silicon at 400 MHz
Signed-off-by: Wolfgang Denk
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Now that we have 3 boards for the MPC512x it turns out that they all
use the very same fixed_sdram() code.This patch factors out this common code into cpu/mpc512x/fixed_sdram.c
and adds a new header file, include/asm-ppc/mpc512x.h, with some
macros, inline functions and prototype definitions specific to MPC512x
systems.Signed-off-by: Wolfgang Denk
Cc: Stefan Roese
Cc: Reinhard Arlt -
The mecp5123 board did not compile because the MSCAN Clock Control
Registers were missing; these got added, but as an array instead
of 4 individual registers. Adapt the code so it builds.Signed-off-by: Wolfgang Denk
Cc: Stefan Roese
Cc: Reinhard Arlt -
Signed-off-by: Wolfgang Denk
Cc: Stefan Roese
Cc: Reinhard Arlt -
When enabling NAND support for a board, one must also define
CONFIG_SYS_64BIT_VSPRINTF because this is needed in nand_util.c
for correct output.Signed-off-by: Wolfgang Denk
Cc: Stefan Roese
Cc: Reinhard Arlt
13 Jul, 2009
3 commits
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For JEDEC flash, we should issue word programming command relative to
base address rather than sector base address. Original source makes
SST Flash fails to program sectors which are not on the 0x10000 boundaries.e.g.
SST39LF040 uses addr1=0x5555 and addr2=0x2AAA, however, each sector
is 0x1000 bytes.Thus, if we issue command to "sector base (0x41000) + offset(0x5555)",
it sends to 0x46555 and the chip fails to recognize that address.This patch is tested with SST39LF040.
Signed-off-by: Po-Yu Chuang
Signed-off-by: Stefan Roese -
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
Signed-off-by: Peter Pearse
Cc: Catalin Marinas -
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
Signed-off-by: Peter Pearse
Cc: Catalin Marinas
12 Jul, 2009
5 commits
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AT91sam9g10 is an ARM 926ej-s SOC. It is an evolution of the at91sam9261 with a
faster clock speed: 266/133MHz.Signed-off-by: Sedji Gaouaou
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AT91sam9g45 series is an ARM 926ej-s SOC family clocked at 400/133MHz.
It embeds USB high speed host and device, LCD, DDR2 RAM, and a full set of
peripherals.The first board that embeds at91sam9g45 chip is the AT91SAM9G45-EKES.
On the board you can find 2 USART, USB high speed,
a 480*272 LG lcd, ethernet, gpio/joystick/buttons.Signed-off-by: Sedji Gaouaou
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The current defition for CKEN_B register bits is nonsense. Adding 32 to
the shifted value is equal to '| (1 << 5)', and this bit is marked
'reserved' in the PXA docs.Signed-off-by: Daniel Mack
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This clock is needed for systems using the USB2 device unit or the 2d
graphics accelerator.Signed-off-by: Daniel Mack
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Pandora is using both SDRC CSes. The MUX setting is needed
for the second CS clock signal to allow the 2 RAM parts to
be put in self-refresh correctly.Based on similar patch for beagle and overo by
Jean Pihet and Steve Sakoman.
