13 Mar, 2013

1 commit


12 Mar, 2013

1 commit

  • In master we had already taken a patch to fix the davinci GPIO code for
    CONFIG_SOC_DM646X and in u-boot-ti we have additional patches to support
    DA830 (which is CONFIG_SOC_DA8XX && !CONFIG_SOC_DA850). Resolve these
    conflicts manually and comment the #else/#endif lines for clarity.

    Conflicts:
    arch/arm/include/asm/arch-davinci/gpio.h
    drivers/gpio/da8xx_gpio.c

    Signed-off-by: Tom Rini

    Tom Rini
     

11 Mar, 2013

1 commit


09 Mar, 2013

1 commit


04 Mar, 2013

1 commit


22 Feb, 2013

1 commit


21 Feb, 2013

1 commit


19 Feb, 2013

3 commits


16 Feb, 2013

2 commits


15 Feb, 2013

1 commit


12 Feb, 2013

2 commits


07 Feb, 2013

3 commits

  • The board is named pcm051 and has this hardware:
    SOC: TI AM3359
    DDR3-RAM: 2x MT41J256M8HX-15EIT:D 512MiB
    ETH 1: LAN8710AI
    SPI-Flash: W25Q64BVSSIG
    RTC: RV-4162-C7
    I2C-EEPROM: CAT32WC32
    NAND: MT29F4G08_VFPGA63
    PMIC: TPS65910A3
    LCD

    Supported:
    UART 1
    MMC/SD
    ETH 1
    USB
    I2C
    SPI

    Not yet supported:
    NAND
    RTC
    LCD

    Signed-off-by: Lars Poeschel
    [trini: Add #define CONFIG_PHY_ADDR 0 to config]
    Signed-off-by: Tom Rini

    Lars Poeschel
     
  • Even when the IGEPv2 board and the IGEP Computer-on-Module
    are different from a form factor point of view, they are
    very similar in the fact that share many components and how
    they are wired.

    So, it is possible (and better) to have a single board file
    for both devices and just use the CONFIG_MACH_TYPE to make
    a differentiation between each board when needed.

    This change avoids code duplication by removing 298 lines of
    code and makes future maintenance easier.

    Signed-off-by: Javier Martinez Canillas
    Acked-by: Igor Grinberg

    Javier Martinez Canillas
     
  • Enable DCC driver for arm zynq platform to be compiled.

    Signed-off-by: Michal Simek

    Michal Simek
     

03 Feb, 2013

1 commit


31 Jan, 2013

2 commits

  • BSC9132QDS is a Freescale reference design board for BSC9132 SoC.
    BSC9132 SOC is an integrated device that targets the evolving Microcell,
    Picocell, and Enterprise-Femto base station market subsegments.
    It combines Power Architecture e500v2 and DSP StarCore SC3850 core
    technologies with MAPLE-B2F baseband acceleration processing elements.

    BSC9132QDS Overview
    --------------------
    2Gbyte DDR3 (on board DDR), Dual Ranki
    32Mbyte 16bit NOR flash
    128Mbyte 2K page size NAND Flash
    256 Kbit M24256 I2C EEPROM
    128 Mbit SPI Flash memory
    SD slot
    USB-ULPI
    eTSEC1: Connected to SGMII PHY
    eTSEC2: Connected to SGMII PHY
    PCIe
    CPRI
    SerDes
    I2C RTC
    DUART interface: supports one UARTs up to 115200 bps for console display

    Apart from the above it also consists various peripherals to support DSP
    functionalities.

    This patch adds support for mainly Power side functionalities and peripherals

    Signed-off-by: Naveen Burmi
    Signed-off-by: Poonam Aggrwal
    Signed-off-by: Prabhakar Kushwaha
    Signed-off-by: Andy Fleming

    Prabhakar Kushwaha
     
  • B4860QDS is a high-performance computing evaluation, development and
    test platform supporting the B4860 QorIQ Power Architecture processor.

    B4860QDS Overview
    ------------------
    - DDRC1: Ten separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s,
    ECC, 4 GB of memory in two ranks of 2 GB.
    - DDRC2: Five separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s, ECC, 2 GB of memory. Single rank.
    - SerDes 1 multiplexing: Two Vitesse (transmit and receive path) cross-point
    16x16 switch VSC3316
    - SerDes 2 multiplexing: Two Vitesse (transmit and receive path) cross-point
    8x8 switch VSC3308
    - USB 2.0 ULPI PHY USB3315 by SMSC supports USB port in host mode.
    - B4860 UART port is available over USB-to-UART translator USB2SER or over
    RS232 flat cable.
    - A Vitesse dual SGMII phy VSC8662 links the B4860 SGMII lines to 2xRJ-45 copper
    connectors for Stand-alone mode and to the 1000Base-X over AMC MicroTCA
    connector ports 0 and 2 for AMC mode.
    - The B4860 configuration may be loaded from nine bits coded reset
    configuration reset source. The RCW source is set by appropriate
    DIP-switches:
    - 16-bit NOR Flash / PROMJet
    - QIXIS 8-bit NOR Flash Emulator
    - 8-bit NAND Flash
    - 24-bit SPI Flash
    - Long address I2C EEPROM
    - Available debug interfaces are:
    - On-board eCWTAP controller with ETH and USB I/F
    - JTAG/COP 16-pin header for any external TAP controller
    - External JTAG source over AMC to support B2B configuration
    - 70-pin Aurora debug connector
    - QIXIS (FPGA) logic:
    - 2 KB internal memory space including
    - IDT840NT4 clock synthesizer provides B4860 essential clocks : SYSCLK,
    DDRCLK1, 2 and RTCCLK.
    - Two 8T49N222A SerDes ref clock devices support two SerDes port clocks
    - total four refclk, including CPRI clock scheme

    Signed-off-by: York Sun
    Signed-off-by: Prabhakar Kushwaha
    Signed-off-by: Shaveta Leekha
    Signed-off-by: Priyanka Jain
    Signed-off-by: Poonam Aggrwal
    Signed-off-by: Roy Zang
    Signed-off-by: Sandeep Singh
    Signed-off-by: Andy Fleming

    York Sun
     

28 Jan, 2013

1 commit


21 Jan, 2013

1 commit


17 Jan, 2013

2 commits


12 Jan, 2013

2 commits


09 Jan, 2013

1 commit


22 Dec, 2012

1 commit


21 Dec, 2012

1 commit


20 Dec, 2012

3 commits


10 Dec, 2012

1 commit


07 Dec, 2012

1 commit

  • Because calculate_relocation_address now uses the e820 map, it will be able
    to avoid addresses over 32 bits and regions that are at high addresses but
    not big enough for U-Boot. It also means we can remove the hack which
    limitted U-Boot's idea of the size of memory to less than 4GB.

    Also take into account the space needed for the heap and stack, so we avoid
    picking a very small region those areas might overlap with something it
    shouldn't.

    Signed-off-by: Gabe Black
    Signed-off-by: Simon Glass

    Gabe Black
     

06 Dec, 2012

1 commit


28 Nov, 2012

3 commits


14 Nov, 2012

1 commit

  • - update clock settings for higher perfomance
    - change standard baud rate to 115200
    - fix flash base address
    - remove unused defines
    - add I2C support
    - switch form board dependent flash to cfi
    - remove board dependent flash code
    - use sdram bank 0 instead of bank 1 on boot
    - enable on board frame buffer instead external
    - remove fake mac address form config
    - add watchdog support
    - add status led support

    Signed-off-by: Jens Scharsig (BuS Elektronik)
    [agust: fixed small style issues and build warning]
    Signed-off-by: Anatolij Gustschin

    Jens Scharsig (BuS Elektronik)