22 Feb, 2014
3 commits
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Freescale LayerScape SoCs support controller interleaving on 256 byte size.
This interleaving is mandoratory.Signed-off-by: York Sun
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DDR base address has been the same from the view of core and DDR
controllers. This has changed for Freescale ARM-based SoCs. Controllers
setup DDR memory in a contiguous space and cores view it at separated
locations.Signed-off-by: York Sun
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Initially it was believed the DDR controller on Freescale ARM would have
big endian. But some platform will have little endian.Signed-off-by: York Sun
22 Jan, 2014
1 commit
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Existing workaround only handles one RDIMM on reference design. In case
of two RDIMMs being used, the workaround requires two separate writes to
DDR_SDRAM_MD_CNTL register.This patch also restores two debug registers changed by the workaround.
Signed-off-by: York Sun
CC: Ben Collins
CC: James Yang
26 Nov, 2013
5 commits
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The DRAM base has been zero for Power SoCs. It could be non-zero
for ARM SoCs. Use a macro instead of hard-coding to zero.Signed-off-by: York Sun
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Some DDR registers' fields have expanded to accommodate larger values.
These changes are backward compatible. Some fields are removed for newer
DDR controllers. Writing to those fields are safely ignored.TIMING_CFG_2 register is fixed. Additive latency is added to RD_TO_PRE
automatically. It was a misunderstanding in commit c360ceac.Signed-off-by: York Sun
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Make PowerPC specific code conditional so ARM SoCs can reuse
this driver. Add DDR3 driver for ARM.Signed-off-by: York Sun
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Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3
structure for 83xx, 85xx and 86xx.Signed-off-by: York Sun
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Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs.
The similar DDR controllers will be used for ARM-based SoCs.Signed-off-by: York Sun