15 Oct, 2013
1 commit
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Signed-off-by: Wolfgang Denk
[trini: Drop changes for PEP 4 following python tools]
Signed-off-by: Tom Rini
24 Jul, 2013
1 commit
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Signed-off-by: Wolfgang Denk
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini
23 Aug, 2012
1 commit
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This is needed to make room for a bugfix on p1_p2_rdb_pc. A sync is used
before the final write to LSOR that initiates the transaction, to ensure
all the other set up has been completed.Signed-off-by: Scott Wood
Signed-off-by: Andy Fleming
16 Apr, 2011
1 commit
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Change variables to const to reduce code size, these values are
hardcoded via defines anyways so we might as well assume they
are constantsSigned-off-by: Matthew McClintock
cc: Scott Wood
16 Jul, 2010
1 commit
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Currently, 83xx, 86xx, and 85xx have a lot of duplicated code
dedicated to defining and manipulating the LBC registers. Merge
this into a single spot.To do this, we have to decide on a common name for the data structure
that holds the lbc registers - it will now be known as fsl_lbc_t, and we
adopt a common name for the immap layouts that include the lbc - this was
previously known as either im_lbc or lbus; use the former.In addition, create accessors for the BR/OR regs that use in/out_be32
and use those instead of the mismash of access methods currently in play.I have done a successful ppc build all and tested a board or two from
each processor family.Signed-off-by: Becky Bruce
Acked-by: Kim Phillips
Signed-off-by: Kumar Gala
05 Nov, 2009
1 commit
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The nand_boot_fsl_elbc.c is shared between 83xx & 85xx however we should
not be including the immap_83xx.h when building 85xx. We can just get
this all from common.hSigned-off-by: Kumar Gala
22 Aug, 2009
1 commit
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The code copy data from NAND flash block by block, so when
the data length isn't a whole-number multiple of the block
size, it will overlap the rest space.Signed-off-by: Mingkai Hu
Signed-off-by: Scott Wood
24 Jan, 2009
1 commit
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We load the secondary stage u-boot image from NAND to
system memory by nand_load, but we did not flush d-cache
to memory, nor invalidate i-cache before we jump to RAM.
When the system has cache enabled and the TLB/page attribute
of system memory is cacheable, it will cause issues.- 83xx family is using the d-cache lock, so all of d-cache
access is cache-inhibited. so you can't see the issue.
- 85xx family is using d-cache, i-cache enable, partial
cache lock. you will see the issue.This patch fixes the cache issue.
Signed-off-by: Dave Liu
Signed-off-by: Scott Wood
30 Oct, 2008
1 commit
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- Rename lbus83xx_t to fsl_lbus_t and move it to asm/fsl_lbc.h so that it
can be shared by both 83xx and 85xx
- Remove lbus83xx_t and replace it with fsl_lbus_t in all 83xx boards
files which use lbus83xx_t.
- Move FMR, FIR, FCR, FPAR, LTESR from mpc83xx.h to asm/fsl_lbc.h so that
85xx can share them.Signed-off-by: Jason Jin
Signed-off-by: Haiying Wang
Signed-off-by: Scott Wood
19 Oct, 2008
1 commit
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
22 Aug, 2008
1 commit
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It was for debugging purposes, and shouldn't have been left in.
Signed-off-by: Scott Wood
13 Aug, 2008
1 commit
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Note that with older board revisions, NAND boot may only work after a
power-on reset, and not after a warm reset. I don't have a newer board
to test on; if you have a board with a 33MHz crystal, please let me know
if it works after a warm reset.Signed-off-by: Scott Wood