07 Feb, 2019
2 commits
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Now that new SPI NOR layer uses stateless 4 byte opcodes by default,
don't enable SPI_FLASH_BAR. For SPI controllers that cannot support
4-byte addressing, (stm32_qspi.c, fsl_qspi.c, mtk_qspi.c, ich.c,
renesas_rpc_spi.c) add an imply clause to enable SPI_FLASH_BAR so as to
not break functionality.Signed-off-by: Vignesh R
Tested-by: Simon Goldschmidt
Tested-by: Stefan Roese
Tested-by: Horatiu Vultur
Reviewed-by: Jagan Teki
Tested-by: Jagan Teki #zynq-microzed -
SF_DUAL_FLASH claims to enable support for SF_DUAL_STACKED_FLASH and
SF_DUAL_PARALLEL_FLASH. But, in current U-Boot code, grepping for above
enums yield no user and therefore support seems to be incomplete. Remove
these configs so as to avoid confusion.Signed-off-by: Vignesh R
Reviewed-by: Jagan Teki
Tested-by: Jagan Teki #zynq-microzed
06 May, 2016
1 commit
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Spelling corrections for (among other things):
* environment
* override
* variable
* ftd (should be "fdt", for flattened device tree)
* embedded
* FTDI
* emulation
* controller
06 Feb, 2016
1 commit
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Correct spelling of "U-Boot" shall be used in all written text
(documentation, comments in source files etc.).Signed-off-by: Bin Meng
Reviewed-by: Heiko Schocher
Reviewed-by: Simon Glass
Reviewed-by: Minkyu Kang
28 Oct, 2014
1 commit
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Add short documentation-alike note on how to use the Altera SPI
driver with the EPCS/EPCQx1 FPGA IP block on SoCFPGA Cyclone V
into doc/SPI/README.altera_spiSigned-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Pavel Machek
Cc: Jagannadha Sutradharudu Teki
Acked-by: Pavel Machek
Reviewed-by: Jagannadha Sutradharudu Teki
19 Feb, 2014
1 commit
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This shows the log obtained while testing qspi on AM437x board.
Signed-off-by: Sourav Poddar
Reviewed-by: Jagannadha Sutradharudu Teki
13 Jan, 2014
3 commits
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Updated current SPI subsyetem status.
Signed-off-by: Jagannadha Sutradharudu Teki
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This patch added support for accessing dual memories in
parallel connection with single chipselect line from controller.For more info - see doc/SPI/README.dual-flash
Signed-off-by: Jagannadha Sutradharudu Teki
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This patch added support for accessing dual memories in
stacked connection with single chipselect line from controller.For more info - see doc/SPI/README.dual-flash
Signed-off-by: Jagannadha Sutradharudu Teki
11 Jan, 2014
1 commit
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The Faraday FTSSP010 is a multi-function controller
which supports I2S/SPI/SSP/AC97/SPDIF. However This
patch implements only the SPI mode.NOTE:
The DMA and CS/Clock control logic has been altered
since hardware revision 1.19.0. So this patch
would first detects the revision id of the underlying
chip, and then switch to the corresponding software
control routines.Signed-off-by: Kuo-Jung Su
Signed-off-by: Jagannadha Sutradharudu Teki
CC: Tom Rini
19 Dec, 2013
1 commit
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This patch adds a driver for Renesas SoC's Quad SPI bus.
This supports with 8 bits per transfer to use with SPI flash.Signed-off-by: Kouei Abe
Signed-off-by: Nobuhiro Iwamatsu
Signed-off-by: Jagannadha Sutradharudu Teki
10 Dec, 2013
1 commit
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This adds a SPI flash driver which simulates SPI flash clients.
Currently supports the bare min that U-Boot requires: you can
probe, read, erase, and write. Should be easy to extend to make
it behave more exactly like a real SPI flash, but this is good
enough to merge now.sjg@chromium.org added a README and tidied up code a little.
Added a required map_sysmem() for sandbox.Signed-off-by: Mike Frysinger
Signed-off-by: Simon Glass
07 Oct, 2013
3 commits
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Updated SPI/status.txt, with memory_map and TODO.
Signed-off-by: Jagannadha Sutradharudu Teki
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Contains documentation and testing details for qspi flash
interface.Signed-off-by: Sourav Poddar
Reviewed-by: Jagannadha Sutradharudu Teki -
doc/SPI/status.txt added to track the u-boot SPI subsystem status.
Signed-off-by: Jagannadha Sutradharudu Teki