06 Jun, 2017

1 commit

• 457e51cff   common: arm: freescale: layerscape: Move header files out of common.h ... Browse Code »

  We should not have an arch-specific header file in common.h. Adjust the
  board files a little so it is not needed, and drop it.

  Signed-off-by: Simon Glass

  Simon Glass

  2017-06-06 02:12:59 +0800  

26 Aug, 2015

1 commit

• d3963721d   nand: Sync with Linux v4.1 ... Browse Code »

  29

  Update the NAND code to match Linux v4.1. The previous sync was
  from Linux v3.15 in commit 4e67c57125290b25.

  CONFIG_SYS_NAND_RESET_CNT is removed, as the upstream Linux code now
  has its own timeout. Plus, CONFIG_SYS_NAND_RESET_CNT was undocumented
  and not selected by any board.

  Signed-off-by: Scott Wood

  Scott Wood

  2015-08-26 11:53:57 +0800  

24 Apr, 2015

1 commit

• 39b0bbbb2   driver/ifc: Add 64KB page support ... Browse Code »

  IFC has two register pages.Till IFC version 1.4 each
  register page is 4KB each.But IFC ver 2.0 register page
  size is 64KB each.IFC regiters structure is break into
  two viz FCM and RUNTIME.FCM(Flash control machine) registers
  are defined in PAGE0 and controls IFC generic functionality.
  RUNTIME registers are defined in PAGE1 and controls NAND and
  GPCM funcinality.

  FCM and RUNTIME structures defination is common for IFC
  version 1.4 and 2.0.

  Signed-off-by: Jaiprakash Singh
  Signed-off-by: York Sun

  Jaiprakash Singh

  2015-04-24 07:46:50 +0800  

23 Jul, 2014

2 commits

• 591dd1923   driver/nand: Add support of 16K SRAM for IFC 2.0 ... Browse Code »

  Internal SRAM has been incresed from 8KB to 16KB for IFC cotroller ver 2.0.

  Update the page offset calculation logic to support the same.

  Signed-off-by: Prabhakar Kushwaha
  Reviewed-by: York Sun

  Prabhakar Kushwaha

  2014-07-23 07:25:54 +0800  
• 04818bbdc   driver/nand: Update SRAM initialize logic for IFC. ... Browse Code »

  IFC controller v1.1.0 requires internal SRAM initialize by reading
  NAND flash. Higher controller versions have provided "SRAM init" bit in
  NCFGR register space.

  update SRAM initialize logic to reflect the same.

  Also print error message in case of Page read error.

  Signed-off-by: Prabhakar Kushwaha
  Reviewed-by: York Sun

  Prabhakar Kushwaha

  2014-07-23 07:25:54 +0800  

23 Apr, 2014

1 commit

• e77224e2d   driver/fsl_ifc: Add a function to finalize CS0 address binding ... Browse Code »

  For fsl-lsch3 NOR flash boot, IFC CS0 needs to be binded with address
  within 32-bit at fist. After u-boot relocates to DDR, CS0 can be binded
  to higher address to support large space.

  Signed-off-by: York Sun
  CC: Prabhakar Kushwaha

  York Sun

  2014-04-23 08:58:47 +0800  

04 Feb, 2014

1 commit

• 1b4175d6f   driver/ifc:Change accessor function to take care of endianness ... Browse Code »

  IFC registers can be of type Little Endian or big Endian depending upon
  Freescale SoC. Here SoC defines the register type of IFC IP.

  So update acessor functions with common IFC acessor functions to take care
  both type of endianness.

  Signed-off-by: Prabhakar Kushwaha
  Acked-by: York Sun

  Prabhakar Kushwaha

  2014-02-04 00:38:51 +0800  

02 Dec, 2013

1 commit

• 77fdd6d1e   Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx Browse Code »
  Tom Rini

  2013-12-02 21:38:28 +0800  

26 Nov, 2013

1 commit

• 0b66513b2   Driver/IFC: Move Freescale IFC driver to a common driver ... Browse Code »

  Freescale IFC controller has been used for mpc8xxx. It will be used
  for ARM-based SoC as well. This patch moves the driver to driver/misc
  and fix the header file includes.

  Signed-off-by: York Sun

  York Sun

  2013-11-26 03:43:47 +0800