09 Oct, 2018

1 commit


24 Jan, 2018

1 commit


10 Jan, 2018

1 commit

  • Linux bindings have been introduced in the code (removing the U-Boot
    specific ones) without documentation update. Compatible string has
    changed, as well as the four GPIO properties. Reflect this by updating
    the soft-spi.txt documentation.

    Fixes: 102412c415 ("dm: spi: soft_spi: switch to use linux compatible string")
    Signed-off-by: Miquel Raynal
    Reviewed-by: Jagan Teki

    Miquel Raynal
     

13 Dec, 2017

1 commit

  • This patch extends pmic_bind_children prefix matching. In addition to
    the node name the property regulator-name is used while trying to match
    prefixes. This allows assigning different drivers to regulator nodes
    named regulator@1 and regulator@10 for example.
    I have discarded the idea of using other properties then regulator-name
    as I do not see any benefit in using property compatible or even
    regulator-compatible. Of course I am open to change this if there are
    good reasons to do so.

    Signed-off-by: Felix Brack
    Reviewed-by: Simon Glass

    Felix Brack
     

11 Dec, 2017

1 commit

  • Synopsys HSDK clock controller generates and supplies clocks to various
    controllers and peripherals within the SoC.

    Each clock has assigned identifier and client device tree nodes can use
    this identifier to specify the clock which they consume. All available
    clocks are defined as preprocessor macros in the
    dt-bindings/clock/snps,hsdk-cgu.h header and can be used in device
    tree sources.

    Signed-off-by: Eugeniy Paltsev
    Signed-off-by: Alexey Brodkin

    Eugeniy Paltsev
     

01 Dec, 2017

1 commit

  • The reset circuitry in the RK3399 only resets 'almost all logic' when
    a software reset is performed. To make our software maintenance
    easier in the future, we want to have the option (controlled by a DTS
    property) to force all reset causes other than a power-on reset to
    trigger a power-on reset via a GPIO trigger.

    This adds the necessary support to the rk3399-puma (i.e. RK3399-Q7)
    board-support and the documentation for the new property
    (sysreset-gpio) within the /config-node.

    Signed-off-by: Philipp Tomsich
    Tested-by: Klaus Goger
    Reviewed-by: Simon Glass

    Philipp Tomsich
     

30 Nov, 2017

2 commits


26 Nov, 2017

1 commit

  • This DT binding doc is porting from Linux DT binding doc.
    commit 1adcbea4201a6852362aa5ece573f1f169b28113

    Add a device tree bindings document for the SoCFPGA Arria10
    FPGA Manager driver.

    Signed-off-by: Alan Tull
    Acked-by: Rob Herring
    Acked-By: Moritz Fischer
    Signed-off-by: Rob Herring
    Signed-off-by: Tien Fong Chee

    Tien Fong Chee
     

21 Nov, 2017

1 commit


17 Nov, 2017

1 commit


06 Oct, 2017

1 commit


01 Oct, 2017

1 commit

  • It is often desirable to configure the spl-boot-order (i.e. the order
    that SPL probes devices to find the FIT image containing a full U-Boot)
    such that it contains 'the same device the SPL stage was booted from'
    early on. To support this, we introduce the 'same-as-spl' specifier
    for the spl-boot-order property.

    This commit adds:
    - documentation for the new board_spl_was_booted_from() function that
    individual SoCs/boards should provide, if they can determine where
    the SPL was booted from
    - implements the new board_spl_was_booted_from() stub function
    - adds support for handling the 'same-as-spl' specifier and calling
    into the per-SoC/per-board support code.

    This also updates the documentation for the 'u-boot,spl-boot-order'
    property.

    Signed-off-by: Philipp Tomsich
    Reviewed-by: Simon Glass

    Philipp Tomsich
     

22 Sep, 2017

4 commits

  • This driver is adapted from linux drivers/reset/reset-stm32.c
    It's compatible with STM32 F4/F7/H7 SoCs.

    This driver doesn't implement .of_match as it's binded
    by MFD RCC driver.

    To add support for each SoC family, a SoC's specific
    include/dt-binfings/mfd/stm32xx-rcc.h file must be added.

    This patch only includes stm32h7-rcc.h dedicated for STM32H7 SoCs.
    Other SoCs support will be added in the future.

    Signed-off-by: Patrice Chotard
    Reviewed-by: Simon Glass

    Patrice Chotard
     
  • This driver implements basic clock setup, only clock gating
    is implemented.

    This driver doesn't implement .of_match as it's binded
    by MFD RCC driver.

    Files include/dt-bindings/clock/stm32h7-clks.h and
    doc/device-tree-bindings/clock/st,stm32h7-rcc.txt
    will be available soon in a kernel tag, as all the
    bindings have been acked by Rob Herring [1].

    [1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html

    Signed-off-by: Patrice Chotard
    Reviewed-by: Simon Glass

    Patrice Chotard
     
  • This patch adds the ST glue logic to manage the DWC3 HC
    on STiH407 SoC family. It configures the internal glue
    logic and syscfg registers.

    Part of this code been extracted from kernel.org driver
    (drivers/usb/dwc3/dwc3-st.c)

    Signed-off-by: Patrice Chotard
    Reviewed-by: Simon Glass

    Patrice Chotard
     
  • This is the generic phy driver for the picoPHY ports
    used by USB2/1.1 controllers. It is found on STiH407 SoC
    family from STMicroelectronics.

    Signed-off-by: Patrice Chotard
    Reviewed-by: Simon Glass

    Patrice Chotard
     

23 Aug, 2017

1 commit

  • Add i2c driver which can be used on both STM32F7 and STM32H7.
    This I2C block supports the following features:
    _ Slave and master modes
    _ Multimaster capability
    _ Standard-mode (up to 100 kHz)
    _ Fast-mode (up to 400 kHz)
    _ Fast-mode Plus (up to 1 MHz)
    _ 7-bit and 10-bit addressing mode
    _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask)
    _ All 7-bit addresses acknowledge mode
    _ General call
    _ Programmable setup and hold times
    _ Easy to use event management
    _ Optional clock stretching
    _ Software reset

    Signed-off-by: Christophe Kerello
    Signed-off-by: Patrice Chotard
    Reviewed-by: Simon Glass

    Patrice Chotard
     

13 Aug, 2017

1 commit

  • This adds a DRAM controller driver for the RK3368 and places it in
    drivers/ram/rockchip (where the other DM-enabled DRAM controller
    drivers for rockchip devices should also be moved eventually).

    At this stage, only the following feature-set is supported:
    - DDR3
    - 32-bit configuration (i.e. fully populated)
    - dual-rank (i.e. no auto-detection of ranks)
    - DDR3-1600K speed-bin

    This driver expects to run from a TPL stage that will later return to
    the RK3368 BROM. It communicates with later stages through the
    os_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDR
    init code).

    Unlike other DMC drivers for RK32xx and RK33xx parts, the required
    timings are calculated within the driver based on a target frequency
    and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this
    time).

    The RK3368 also has the DDRC0_CON0 (DDR ch. 0, control-register 0)
    register for controlling the operation of its (single-channel) DRAM
    controller in the GRF block. This provides for selecting DDR3, mobile
    DDR modes, and control low-power operation.
    As part of this change, DDRC0_CON0 is also added to the GRF structure
    definition (at offset 0x600).

    Signed-off-by: Philipp Tomsich
    Reviewed-by: Simon Glass

    Philipp Tomsich
     

26 Jul, 2017

1 commit


05 Jun, 2017

3 commits


29 May, 2017

1 commit


12 May, 2017

1 commit


11 May, 2017

2 commits


10 May, 2017

2 commits


08 May, 2017

1 commit


14 Apr, 2017

1 commit


05 Apr, 2017

1 commit

  • The RK3399 does not have any boot selection pins and the BootROM probes
    the boot interfaces using the following boot-order:
    1. SPI
    2. eMMC (sdhci in DTS)
    3. SD card (sdmmc in DTS)
    4. USB loader
    For ease of deployment, the SPL stage should mirror the boot order of
    the ROM and use the same probing order (assuming that valid images can
    be detected by SPL) unless instructed otherwise. The boot-order can
    then be configured via the 'u-boot,spl-boot-order' property in the
    chosen-node of the DTS.

    While this approach is easily extensible to other boards, it is only
    implemented for the RK3399 for now, as the large SRAM on the RK3399
    makes this easy to fit the needed infrastructure into SPL and our
    production setup already runs with DM, OF_CONTROL and BLK in SPL.

    The new boot-order property is expected to be used in conjunction with
    FIT images (and all legacy image formats disabled via Kconfig).

    A boot-sequence with probing and fallthroughs from SPI via eMMC to SD
    card (i.e. &spiflash, &sdhci, &sdmmc) has been validated on the RK3399-Q7.

    Signed-off-by: Philipp Tomsich
    Tested-by: Klaus Goger
    Tested-by: Philipp Tomsich
    Acked-by: Simon Glass

    Philipp Tomsich
     

26 Mar, 2017

1 commit

  • This patch adds support for having a "fixed-link" to some other MAC
    (like some embedded switch-device).

    For this purpose we introduce a new phy-driver, called "Fixed PHY".

    Fixed PHY works only with CONFIG_DM_ETH enabled, since the fixed-link is
    described with a subnode below ethernet interface.

    Most ethernet drivers (unfortunately not all are following same scheme
    for searching/attaching phys) are calling "phy_connect(...)" for getting
    a phy-device.
    At this point we link in, we search here for a subnode called "fixed-
    link", once found we start phy_device_create(...) with the special phy-
    id PHY_FIXED_ID (0xa5a55a5a).

    During init the "Fixed PHY" driver has registered with this id and now
    gets probed, during probe we get all the details about fixed-link out of
    dts, later on the phy reports this values.

    Signed-off-by: Hannes Schmelzer

    Signed-off-by: Hannes Schmelzer
    Acked-by: Joe Hershberger
    Reviewed-by: Christian Gmeiner

    Hannes Schmelzer
     

24 Mar, 2017

2 commits

  • This replaces legacy arch/arc/lib/timer.c implementation and allows us
    to describe ARC Timers in Device Tree. Among other things that way we
    may properly inherit Timer's clock from CPU's clock s they really run
    synchronously.

    Tom Rini
     
  • This commit introduces timer driver for ARC.

    ARC timers are configured via ARC AUX registers so we use special
    functions to access timer control registers.

    This driver allows utilization of either timer0 or timer1
    depending on which one is available in real hardware. Essentially
    only existing timers should be mentioned in board's Device Tree
    description.

    Signed-off-by: Vlad Zakharov
    Reviewed-by: Simon Glass

    Vlad Zakharov
     

23 Mar, 2017

2 commits

  • The USB device should linked to VBUS regulator through "vbus-supply"
    DTS property.
    This patch adds handling for "vbus-supply" property inside the USB
    device entry for turning on the VBUS regulator upon the host adapter probe.

    Signed-off-by: Konstantin Porotchkin
    Cc: Stefan Roese
    Cc: Marek Vasut
    Cc: Nadav Haklai
    Cc: Neta Zur Hershkovits
    Cc: Igal Liberman
    Cc: Haim Boot
    Acked-by: Marek Vasut
    Signed-off-by: Stefan Roese

    Konstantin Porotchkin
     
  • Add support for "marvell,reset-gpio" property to mvebu DW PCIe
    driver.
    This option is valid when CONFIG_DM_GPIO=y

    Change-Id: Ic17c500449050c2fbb700731f1a9ca8b83298986
    Signed-off-by: Konstantin Porotchkin
    Signed-off-by: Rabeeh Khoury
    Cc: Stefan Roese
    Cc: Nadav Haklai
    Cc: Neta Zur Hershkovits
    Cc: Igal Liberman
    Cc: Haim Boot
    Signed-off-by: Stefan Roese

    Konstantin Porotchkin
     

21 Mar, 2017

2 commits


18 Mar, 2017

1 commit