19 Jan, 2009
3 commits
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Update CHANGELOG
Signed-off-by: Wolfgang Denk
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The x86 based version of Darwin behaves the same quirky way as the powerpc
Darwin, so only check HOSTOS when setting up Darwin workarounds.Signed-off-by: Mike Frysinger
18 Jan, 2009
1 commit
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The code in fdt_resize() to extend the fdt size to end on a page boundary
is wrong for fdt's not located at an address aligned on a page boundary.
What's even worse, the code would make actualsize shrink rather than grow
if (blob & 0xfff) was bigger than the amount of padding added by ALIGN(),
causing fdt_add_mem_rsv to fail.Fix it by aligning end address (blob + size) to a page boundary instead.
For aligned fdt's this is equivalent to what we had before.Signed-off-by: Peter Korsgaard
16 Jan, 2009
11 commits
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The recvfrom() function takes a socklen_t, not an int.
Signed-off-by: Mike Frysinger
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
Signed-off-by: Nobuhiro Iwamatsu -
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
Signed-off-by: Nobuhiro Iwamatsu -
lowlevel_init of SH was corrected to use the write/readXX macro.
However, there was a problem that was not able to be compiled partially.
This patch corrected this.Signed-off-by: Nobuhiro Iwamatsu
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Fix up rsk7203 target to build successfully using out-of-tree build.
Signed-off-by: Kieran Bingham
Signed-off-by: Nobuhiro Iwamatsu -
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
Signed-off-by: Nobuhiro Iwamatsu -
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
Signed-off-by: Nobuhiro Iwamatsu -
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
Signed-off-by: Nobuhiro Iwamatsu -
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
Signed-off-by: Nobuhiro Iwamatsu
15 Jan, 2009
2 commits
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Update CHANGELOG.
Signed-off-by: Wolfgang Denk
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Parallel builds would occasionally issue this build warning:
ln: creating symbolic link `cpu/mpc824x/bedbug_603e.c': File exists
Use "ln -sf" as quick work around for the issue.
Signed-off-by: Wolfgang Denk
14 Jan, 2009
13 commits
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This patch adds esd's loadpci BSP command to CPCI4052 and
CPCI405AB board. This requires CONFIG_CMD_BSP and CONFIG_PRAM.Signed-off-by: Matthias Fuchs
Signed-off-by: Stefan Roese -
Signed-off-by: Matthias Fuchs
Signed-off-by: Stefan Roese -
This patch cleans up CPCI405 board support:
- wrap long lines
- unification of spaces in function calls
- remove dead codeUse correct io accessors on peripherals.
Signed-off-by: Matthias Fuchs
Signed-off-by: Stefan Roese -
This patch turns on the auto RS485 mode in the 2nd external
uart on PLU405 boards. This is a special mode of the used
Exar XR16C2850 uart. Because these boards only have a 485 physical
layer connected it's a good idea to turn it on by default.Signed-off-by: Matthias Fuchs
Signed-off-by: Stefan Roese -
- Move the TLB entry of PIXIS_BASE from TLB0 to TLB1[8], because in CAMP mode,
all the TLB0 entries will be invalidated after cpu1 brings up kernel, thus cpu0
can not access PIXIS_BASE anymore (any access will cause DataTLBError exception)- Set CONFIG_SYS_DDR_TLB_START to 9 for MPC8572DS board.
Signed-off-by: Haiying Wang
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So that we can locate the DDR tlb start entry to the value other than 8. By
default, it is still 8.Signed-off-by: Haiying Wang
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The IO port selection for MPC8544DS board:
Port cfg_io_ports
PCIE1 0x2, 0x3, 0x4, 0x5, 0x6, 0x7
PCIE2 0x4, 0x5, 0x6, 0x7
PCIE3 0x6, 0x7
This patch changes the PCIE12 and PCIE2 logic more readable.
Signed-off-by: Roy Zang -
PCIE2 and PCIE3 should be decided by corresponing bit in devdisr instead of
PCIE1 bit.
On MPC8572DS board, PCIE refers to PCIE1.
Signed-off-by: Roy Zang -
The IO port selection is not correct on MPC8572DS and MPC8544DS board.
This patch fixes this issue.
For MPC8572
Port cfg_io_ports
PCIE1 0x2, 0x3, 0x7, 0xb, 0xc, 0xf
PCIE2 0x3, 0x7
PCIE3 0x7For MPC8544
Port cfg_io_ports
PCIE1 0x2, 0x3, 0x4, 0x5, 0x6, 0x7
PCIE2 0x4, 0x5, 0x6, 0x7
PCIE3 0x6, 0x7
Signed-off-by: Roy Zang -
Rename _BASE to _BUS, as it's actually a PCI bus address,
separate virtual and physical addresses into _VIRT and _PHYS,
and use each appopriately. This makes the code easier to read
and understand, and facilitates mapping changes going forward.Signed-off-by: Becky Bruce
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Rename _BASE to _BUS, as it's actually a PCI bus address,
separate virtual and physical addresses into _VIRT and _PHYS,
and use each appopriately. This makes the code easier to read
and understand, and facilitates mapping changes going forward.Signed-off-by: Becky Bruce
12 Jan, 2009
1 commit
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Signed-off-by: Wolfgang Denk
11 Jan, 2009
1 commit
07 Jan, 2009
8 commits
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The board_nand_init() function should return an int, not void.
Signed-off-by: Mike Frysinger
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The eeprom SPI init functions are duplicated as the common code already
executes these for us.Signed-off-by: Mike Frysinger
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Many of the Blackfin board linker scripts are preprocessed, so make sure we
output the linker script into the build tree rather than the source tree.Signed-off-by: Mike Frysinger
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Make sure all .text sections get pulled in and the entry point is properly
referenced so they don't get discarded when linking with --gc-sections.Signed-off-by: Mike Frysinger
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In order to boot an LDR out of parallel flash, the ldr utility needs a few
flags to tell it to generate the right header.Signed-off-by: Mike Frysinger
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD