03 May, 2016
1 commit
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Signed-off-by: Vagrant Cascadian
Reviewed-by: Simon Glass
20 Apr, 2016
10 commits
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The code uses a lot of signed numbers, which ended up in variables
of unsigned type, which resulted in all sorts of underflows. This
in turn caused incorrect calibration on certain boards. Moreover,
repair the readout of the DQ delay, which was being pulled from
wrong register.Signed-off-by: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See -
Just staticize global variables in sequencer, since there is no
point in having these symbols available outside of the DDR code.Signed-off-by: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See -
Originally, the DLEVEL selects the debug level within the sequencer code,
but only displays the messages on that particular debug level. Tweak the
handling such that for particular debug level, debug messages on that
level and lower are displayed. This allows better regulation of debug
message verbosity.Signed-off-by: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See -
This one last set of delay configuration registers was not properly
zeroed out originally, fix it and zero them out.Signed-off-by: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See -
There is no point in resetting the ODT setting if the write test
failed, since the code will always retry the calibration and thus
reconfigure the ODT anyway OR the code will fail calibration and
halt.Signed-off-by: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See -
Every invocation of the scc_mgr_set_dqs_en_delay_all_ranks() is
followed by SCC manager update. Moreover, only this function
triggers the SCC manager update internally. Thus, remove the
internal invocation to avoid triggering the update twice.Signed-off-by: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See -
The hi address bitfield in the protection rule must be set to
the last address in the region which the rule represents. The
behavior is now in-line with code generated by Quartus 15.1 .Signed-off-by: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See -
The code should be setting registers to zero, not one register to value.
Swap the order of arguments to correct the behavior. The behavior is now
in-line with code generated by Quartus 15.1 .Signed-off-by: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See -
In the most unlikely case the DQS tracking was to be disabled,
make sure we do not errornously re-enable it. Note that DQS
tracking is enabled on all systems observed thus far.Signed-off-by: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See -
The bit 22 is in fact DQS tracking enable bit (dqstrken) and there
is a macro for this bit already, so use it.Signed-off-by: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
27 Mar, 2016
1 commit
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Minor change: chosen is written with one "o".
No code change here, only comment & printf.Signed-off-by: Alexander Merkle
Reviewed-by: Bin Meng
24 Mar, 2016
1 commit
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Armada 38x has a maximum of two cores. Probably copy/paste
bug from Armada XP.Signed-off-by: Dirk Eibach
Signed-off-by: Stefan Roese
22 Mar, 2016
2 commits
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During initial DDR training, false parity errors may be detected.
This patch adds workaround to fix the erratum.
Tested on LS2085QDS and LS2080RDB.Signed-off-by: Shengzhou Liu
Reviewed-by: York Sun -
Add support of address parity for DDR4 UDIMM or discrete memory.
It requires to configurate corresponding MR5[2:0] and
TIMING_CFG_7[PAR_LAT]. Parity can be turned on by hwconfig,
e.g. hwconfig=fsl_ddr:parity=on.Signed-off-by: Shengzhou Liu
Reviewed-by: York Sun
06 Feb, 2016
1 commit
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Correct spelling of "U-Boot" shall be used in all written text
(documentation, comments in source files etc.).Signed-off-by: Bin Meng
Reviewed-by: Heiko Schocher
Reviewed-by: Simon Glass
Reviewed-by: Minkyu Kang
02 Feb, 2016
1 commit
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This driver initializes PIC32 DDR2 SDRAM controller and internal DDR2 Phy module.
DDR2 controller operates in half-rate mode (upto 533MHZ frequency).Signed-off-by: Paul Thacker
Signed-off-by: Purna Chandra Mandal
Reviewed-by: Daniel Schwierzeck
Reviewed-by: Tom Rini
Reviewed-by: Simon Glass
26 Jan, 2016
3 commits
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Following commit 61bd2f75, exclude unused DDR controller from
calculating RAM size for SPL boot.Signed-off-by: Ed Swarthout
Reviewed-by: York Sun -
Erratum A-009663 workaround requires to set DDR_INTERVAL[BSTOPRE] to 0
before setting DDR_SDRAM_CFG[MEM_EN] and set DDR_INTERVAL[BSTOPRE]
to the desired value after DDR initialization has completed.When DDR controller is configured to operate in auto-precharge
mode(DDR_INTERVAL[BSTOPRE]=0), this workaround is not needed.Signed-off-by: Shengzhou Liu
Reviewed-by: York Sun -
During the receive data training, the DDRC may complete on a
non-optimal setting that could lead to data corruption or
initialization failure.Workaround: before setting MEM_EN, set DEBUG_29 register with
specific value for different data rates.Signed-off-by: Shengzhou Liu
Reviewed-by: York Sun
19 Jan, 2016
1 commit
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In a number of places we had wordings of the GPL (or LGPL in a few
cases) license text that were split in such a way that it wasn't caught
previously. Convert all of these to the correct SPDX-License-Identifier
tag.Signed-off-by: Tom Rini
16 Jan, 2016
1 commit
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Init the rule ID, otherwise the debug code will always dump the
protection settings entry 0.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Dinh Nguyen
14 Jan, 2016
4 commits
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This should make it clear that this symbol is meant to be defined by
board headers.Signed-off-by: Phil Sutter
Acked-by: Stefan Roese
Reviewed-by: Tom Rini -
If MV_DEBUG_WL is defined, DEBUG_WL_S and DEBUG_WL_D macros are missing.
In addition to that, get rid of debug output printing non-existent
counter variable.Signed-off-by: Phil Sutter
Acked-by: Stefan Roese
Reviewed-by: Tom Rini -
Currently, ECC support is enabled for all Armada XP boards. So the
DDR3 driver tries to configure the controller with ECC support, even
on boards without ECC. This patch makes this ECC optional which now
can be configured on a board-per-board basis.Signed-off-by: Stefan Roese
Cc: Luka Perkov
Cc: Phil Sutter -
gcc 5.1 generates this new warning (for Armada 38x platforms):
drivers/ddr/marvell/a38x/ddr3_debug.c: In function 'hws_ddr3_tip_read_training_result':
drivers/ddr/marvell/a38x/ddr3_debug.c:177:40: warning: 'sizeof' on array
function parameter 'result' will return size of 'enum hws_result (*)[1]' [-Wsizeof-array-argument]
memcpy(result, training_result, sizeof(result));
^
drivers/ddr/marvell/a38x/ddr3_debug.c:171:31: note: declared here
u32 dev_num, enum hws_result result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM])
^Since this functions is not referenced anywhere, lets just remove it.
Signed-off-by: Stefan Roese
Cc: Luka Perkov
15 Dec, 2015
1 commit
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As the errata A008336 and A008514 do not apply to all LS series SoCs
(such as LS1021A, LS1043A) we move them to an soc specific fileSigned-off-by: Yuan Yao
Reviewed-by: York Sun
14 Dec, 2015
6 commits
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DDR errata-A008378 applies to LS1021-20-22A-R1.0, T1023-R1.0,
T1024-R1.0, T1040-42-20-22-R1.0/R1.1, it has been fixed on
LS102x Rev2.Signed-off-by: Shengzhou Liu
Reviewed-by: York Sun -
In case four chip-selects are all active, the turnaround times need to
increase to avoid overlapping under heavy load.Signed-off-by: York Sun
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The workaround requires different setting for range 1 vs 2.
Also adjust timeout value for waiting for controller to be idle.Signed-off-by: York Sun
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For four chip-selects enabled case, RTT is parked on all of them.
Signed-off-by: York Sun
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MR6 bit 6 is set accrodingly for range 1 or 2, per JEDEC spec.
Signed-off-by: York Sun
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DDR4 has different RTT value and code according to JEDEC spec. Update
the macros and options .Signed-off-by: York Sun
01 Dec, 2015
4 commits
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BIST test code has a typo, resulting the binding registers not
maintained as expected. This typo results BIST runs twice on
the covered memory.Signed-off-by: York Sun
Reported-by: Shengzhou Liu -
Freescale LSCH3 platforms use two DDR controlers interleaving mode out of
reset. It can be configured to disable one controller. To support this
operation, the driver needs to detect and skip the disabled controller.Signed-off-by: York Sun
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Freescale's LS2085A is a another personality of LS2080A SoC with
support of AIOP and DP-DDR.
This Patch adds support of LS2085A Personality.Signed-off-by: Pratiyush Mohan Srivastava
Signed-off-by: Prabhakar Kushwaha
[York Sun: Updated MAINTAINERS files
Dropped #ifdef in cpu.h
Add CONFIG_SYS_NS16550=y in defconfig]
Reviewed-by: York Sun -
LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP
personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc.
So renaming existing LS2085A code base to reflect LS2080A (Prime personality)Signed-off-by: Pratiyush Mohan Srivastava
Signed-off-by: Prabhakar Kushwaha
[York Sun: Dropped #ifdef in cpu.c for cpu_type_list]
Reviewed-by: York Sun
18 Nov, 2015
2 commits
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SAR1_CPU_CORE_MASK was wrong, probably copy/paste
from another architecture.Signed-off-by: Dirk Eibach
Reviewed-by: Stefan Roese -
A lot of extra configuration information was left over in the
Marvell serdes and DDR3 initialization code for boards that
U-boot does not support. Remove this extra config information,
and the concept of fixing up board topologies with information
loaded from an EEPROM. If this needs to be done, it should be
handled in the board file, not in core code.Signed-off-by: Kevin Smith
Acked-by: Stefan Roese
Cc: Dirk Eibach
Cc: Luka Perkov
10 Nov, 2015
1 commit
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After consulting with some of the SPDX team, the conclusion is that
Makefiles are worth adding SPDX-License-Identifier tags too, and most of
ours have one. This adds tags to ones that lack them and converts a few
that had full (or in one case, very partial) license blobs into the
equivalent tag.Cc: Kate Stewart
Signed-off-by: Tom Rini