31 Mar, 2017
1 commit
17 Aug, 2016
1 commit
30 May, 2016
1 commit
-
Commit 6ca5f482a38ce ("driver: net: cpsw: add support for RGMII id mode
support and RMII clock source selection") enables the external chip clock
for RMII mode using private data. This data needs to be populated from
DT data. The above commit misses populating this data.Signed-off-by: Lokesh Vutla
26 May, 2016
1 commit
-
Commit 6ca5f482a38ce ("driver: net: cpsw: add support for RGMII id mode
support and RMII clock source selection") missed update for am43xx variants.
Updating it here.Fixes: 6ca5f482a38ce ("driver: net: cpsw: add support for RGMII id mode support and RMII clock source selection")
Reported-by: Roger Quadros
Signed-off-by: Lokesh Vutla
25 May, 2016
1 commit
-
The index returned by get_sys_clk_index() is not exactly what we expect.
Let's not rely on that and use get_sys_clk_freq() instead.This fixes missing USB3 devices in the Linux kernel when USB is started
in u-boot. It still doesn't fix missing USB3 devices in u-boot though.Signed-off-by: Roger Quadros
23 May, 2016
1 commit
-
In the current driver implementation, config() callback is common
for AR8035 and AR8031 phy. In config() callback, driver tries to
configure MMD Access Control Register and MMD Access Address Data
Register unconditionally for both phy versions which leads to
auto negotiation failure in AM335x EVMsk second port which uses
AR8031 Giga bit RGMII phy. Fixing this by adding separate config
for AR8031 phy.Reviewed-by: Sekhar Nori
Signed-off-by: Mugunthan V N
19 May, 2016
1 commit
-
cpsw driver supports only selection of phy mode in control module
but control module has more setting like RGMII ID mode selection,
RMII clock source selection. So ported to cpsw-phy-sel driver
from kernel to u-boot.Signed-off-by: Mugunthan V N
17 May, 2016
1 commit
-
* 'master' of git://git.denx.de/u-boot: (31 commits)
Prepare v2016.05
sunxi: Enable USB host in CHIP defconfig
test, tools: update tbot documentation
tests: py: fix NameError exception if bdi cmd is not supported
arm/arm64: Move barrier instructions into separate header
arm: socfpga: Update iomux and pll for c5 socdk RevE
warp7: Fix boot by selecting CONFIG_OF_LIBFDT
usb: gadget: dfu: discard dead code
dfu: avoid memory leak
usb: dwc2: Add delay to fix the USB detection problem on SoCFPGA
usb: hub: Don't continue on get_port_status failure
usb: Assure Get Descriptor request is in separate microframe
usb: Wait after sending Set Configuration request
socfpga: fix broken build if CONFIG_ETH_DESIGNWARE disabled
mtd: cqspi: Simplify indirect read code
mtd: cqspi: Simplify indirect write code
arm: socfpga: socrates: Add 'time' command
ARM: socfpga: Disable USB OC protection on SoCrates
usb: Don't init pointer to zero, but NULL
usb: ehci-mx6: allow board_ehci_hcd_init to fail
...Signed-off-by: Lokesh Vutla
07 May, 2016
8 commits
-
Reported by Coverity:
Logically dead code (DEADCODE)
dead_error_line: Execution cannot reach this statement:
(f_dfu->strings + --i).s = ....If calloc failed, i is still 0 and no need to call free,
so discard the dead code.Signed-off-by: Peng Fan
Cc: "Łukasz Majewski"
Cc: Marek Vasut -
When dfu_fill_entity fail, need to free dfu to avoid memory leak.
Reported by Coverity:
"
Resource leak (RESOURCE_LEAK)
leaked_storage: Variable dfu going out of scope leaks the storage
it points to.
"Signed-off-by: Peng Fan
Cc: "Łukasz Majewski"
Cc: Marek Vasut -
With patch c998da0d (usb: Change power-on / scanning timeout handling),
the USB scanning is started earlier and with a smaller timeout. This
resulted on SoCFPGA (using the DWC2 driver) in some USB sticks not
getting detected any more. This patch now adds a 1 second delay (in
the host mode only) to the DWC2 driver before the scanning is started.
With this delay, now all problematic USB keys are detected successfully
again. And there is no need any more to change the delay / timeout
in the common USB code (usb_hub.c).Signed-off-by: Stefan Roese
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Hans de Goede
Cc: Stephen Warren
Cc: Marek Vasut -
The indirect read code is a pile of nastiness. This patch replaces
the whole unmaintainable indirect read implementation with the one
from upcoming Linux CQSPI driver, which went through multiple rounds
of thorough review and testing. All the patch does is it plucks out
duplicate ad-hoc code distributed across the driver and replaces it
with more compact code doing exactly the same thing. There is no
speed change of the read operation.Signed-off-by: Marek Vasut
Cc: Anatolij Gustschin
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Jagan Teki
Cc: Pavel Machek
Cc: Stefan Roese
Cc: Vignesh R -
The indirect write code is buggy pile of nastiness which fails horribly
when the system runs fast enough to saturate the controller. The failure
results in some pages (256B) not being written to the flash. This can be
observed on systems which run with Dcache enabled and L2 cache enabled,
like the Altera SoCFPGA.This patch replaces the whole unmaintainable indirect write implementation
with the one from upcoming Linux CQSPI driver, which went through multiple
rounds of thorough review and testing. While this makes the patch look
terrifying and violates all best-practices of software development, all
the patch does is it plucks out duplicate ad-hoc code distributed across
the driver and replaces it with more compact code doing exactly the same
thing.Signed-off-by: Marek Vasut
Cc: Anatolij Gustschin
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Jagan Teki
Cc: Pavel Machek
Cc: Stefan Roese
Cc: Vignesh R -
There could be runtime determined board specific reason why a EHCI
initialization fails (e.g. ENODEV if a Port is not available). In
this case, properly return the error code.
While at it, that function (board_ehci_hcd_init) has actually two
documentation blocks... Use the correct function name for the
documentation block of board_usb_phy_mode.Signed-off-by: Stefan Agner
06 May, 2016
24 commits
-
There is no for Keystone so
don't include it for Keystone.Signed-off-by: Roger Quadros
Signed-off-by: Lokesh Vutla
Signed-off-by: Mugunthan V N -
gpmc driver is used by non OMAP SoCs from TI so move it
to a more generic location.Signed-off-by: Roger Quadros
Signed-off-by: Lokesh Vutla
Signed-off-by: Mugunthan V N -
Adopt usb ether gadget and rndis driver to adopt driver model
Signed-off-by: Mugunthan V N
-
prepare driver for driver model migration
Signed-off-by: Mugunthan V N
-
Use net device priv to pass usb ether priv and use it in
net device ops callback.Signed-off-by: Mugunthan V N
-
Consolidate the net device, usb eth device and gadget device
struct to single struct and a single global variable so that the
same can be passed as priv of ethernet driver.Signed-off-by: Mugunthan V N
-
network_started of struct eth_dev can be accessed using local
variable dev and no reason to access it with the global struct.Signed-off-by: Mugunthan V N
-
Convert usb ether gadget to adopt usb driver model
Signed-off-by: Mugunthan V N
-
Add a TI MUSB peripheral driver with driver model support and the
driver will be bound by the MUSB wrapper driver based on the
dr_mode device tree entry.Signed-off-by: Mugunthan V N
-
Add a TI MUSB host driver with driver model support and the
driver will be bound by the MUSB wrapper driver based on the
dr_mode device tree entry.Signed-off-by: Mugunthan V N
-
Currently all backend driver ops uses hard coded physical
address, so to adopt the driver to DM, add device pointer to ops
call backs so that drivers can get physical addresses from the
usb driver priv/plat data.Signed-off-by: Mugunthan V N
-
Add a misc driver for MUSB wrapper, so that based on dr_mode the
USB devices can bind to USB host or USB device drivers.Signed-off-by: Mugunthan V N
-
Add common usb code which usb drivers makes use of it.
Signed-off-by: Mugunthan V N
-
Since AM572x SR1.1 has erratas to limit the frequency of MMC1 to
96MHz and frequency of MMC2 to 48MHz for AM572x SR1.1 and the driver
doesn't handle variable frequencies for MMC1 and MMC2, disable higher
speed modes for SR1.1Signed-off-by: Kishon Vijay Abraham I
-
From OMAP3 SoCs (OMAP3, OMAP4, OMAP5, AM572x, AM571x), the DAT/CMD lines
reset procedure section in TRM suggests to first poll the SRD/SRC bit
until it is set to 0x1. But looks like that bit is never set to 1 and there
is an observable delay of 1sec everytime the driver tries to reset DAT/CMD.
(The same is observed in linux kernel).Reduce the time the driver waits for the controller to set the SRC/SRD bits
to 1 so that there is no observable delay.TODO: Debug why the SRC/SRD bits are never set
Signed-off-by: Kishon Vijay Abraham I
-
Instead of sending STOP TRANSMISSION command from MMC core, enable
the auto command feature so that the Host Controller issues CMD12
automatically when last block transfer is completed.Signed-off-by: Kishon Vijay Abraham I
-
According to errata i802, DCRC error interrupts
(MMCHS_STAT[21] DCRC=0x1) can occur during the tuning procedure.The DCRC interrupt, occurs when the last tuning block fails
(the last ratio tested). The delay from CRC check until the
interrupt is asserted is bigger than the delay until assertion
of the tuning end flag. Assertion of tuning end flag is what
masks the interrupts. Because of this race, an erroneous DCRC
interrupt occurs.The suggested workaround is to disable DCRC interrupts during
the tuning procedure which is implemented here.TODO: Debug why other error interrupts are received during
tuning.Signed-off-by: Kishon Vijay Abraham I
-
The data manual of J6/J6 Eco recommends to set different IODELAY values
depending on the mode in which the MMC/SD is enumerated in order to
ensure IO timings are met.Add support to parse mux values and iodelay values from device tree
and set these depending on the enumerated MMC mode.Signed-off-by: Kishon Vijay Abraham I
-
Find the compatible string match based on the order in which
it is populated in the device tree node rather than matching
based on the order in which it is populated in the drivers match
table.
This is required in order to get the right driver data.Signed-off-by: Kishon Vijay Abraham I
-
omap hsmmc host controller has ADMA2 feature. Enable it here
for better read and write throughput.Signed-off-by: Kishon Vijay Abraham I
-
Use the mmc_of_parse library function to populate mmc_config instead of
repeating the same code in host controller driver.Signed-off-by: Kishon Vijay Abraham I
-
HS200/SDR104 requires tuning command to be sent to the card. Use
the mmc_send_tuning library function to send the tuning
command and configure the internal DLL.Signed-off-by: Kishon Vijay Abraham I
-
In order to enable DDR mode, Dual Data Rate mode bit has to be
set in MMCHS_CON register. Set it here.Signed-off-by: Kishon Vijay Abraham I
-
Use the timing parameter set in the MMC core to set the
mode in UHSMS bit field. This is in preparation for
adding HS200 support in omap hsmmc driver.Signed-off-by: Kishon Vijay Abraham I
