Eric Lee / linux-smarc-t335x-v3.2

14 Feb, 2014

35 commits

14 Jun, 2013

3 commits

  • d5720d33b   ARM: OMAP2+: AM335x: update OPP50 handling ... Browse Code »

    Recent commit from Greg (OPP Table fix for 720MHZ and ZCE
    support) added OPP120 support for PG 2.x.

    OPP120 support needs to be disabled when the board is booted and
    running at OPP50. This is as per the Advisory 1.0.15 (ARM Cortex-A8:
    OPP50 Operation on MPU Domain Not Supported)

    Voltage checked here are Core Voltage and not MPU. Hence, When here
    correct the preprocessors to indicate correct voltages.

    As per Sitara AM335x ARM Cortex -A8 Microprocessors (MPUs) data sheet
    (SPRS717F) APRIL 2013 available at
    http://www.ti.com/lit/ds/symlink/am3359.pdf

    Table 3-7 and 3-9 has been updated to show the defined OPPs on ZCZ and
    ZCE packages respectively

    Signed-off-by: Hebbar Gururaja

    Hebbar Gururaja
     
  • 97bdb69b0   OPP Table fix for 720MHZ and ZCE support ... Browse Code »

    Current OPP table excludes 720MHz OPPs for ES 2.0 and ES 2.1. It also
    excludes an 300MHz at 1.1V operating point required for ZCE support on
    ES 2.1.
    This patch implements support for the same.

    As per Sitara AM335x ARM Cortex -A8 Microprocessors (MPUs) data sheet
    (SPRS717F) APRIL 2013 available at
    http://www.ti.com/lit/ds/symlink/am3359.pdf

    Table 3-7 and 3-9 has been updated to show the defined OPPs on ZCZ and
    ZCE packages respectively

    [ Hebbar Gururaja]:
    - Add Link to Documentation and reference table.
    - Fix merge issue and remove whitespace warning

    Signed-off-by: Greg Guyotte
    Signed-off-by: Hebbar Gururaja

    Greg Guyotte
     
  • bdb7a2449   ARM: OMAP2+: AM33XX: Fix race between request_irq and gpio_mask_irq ... Browse Code »

    After random iteration, uart standby using (gpio pin configs) hangs.

    Upon deep observation (and lots of debug prints), it was observed that
    the GPIO Rising/Falling detect registers were cleared (IRQ disabled)
    before system entered standby. Any UART activity (key press) was not
    detected.

    This registers were properly setup by request_irq call from
    am33xx_pm_prepare_late() (initial suspend stage).

    However, driver suspend calls (.suspend()) come in later stage and due
    to some race condition, gpio_mask_irq() masks/clears above registers.

    The fix is to call the standby setup function (which calls request_irq)
    at final stage just before the actual suspend call.

    This fix was tested by placing the system under standby stress test for
    more than 20 Hours.

    Signed-off-by: Hebbar Gururaja

    Hebbar Gururaja
     

05 Jun, 2013

2 commits

  • 8d78a2001   ARM: OMAP: AM33XX: Add OPP table for PG2.1 AM335x ... Browse Code »

    Add OPP table for MPU voltage domain.

    Changes from PG2.0:
    1. The Operating voltage for Nitro Mode is 1.35V
    2. PG 2.1 SoC has a new efuse sma register which describes the device's
    ARM maximum frequency capabilities and package type. Upon parsing this
    register, the supported maximum frequency is obtained.
    Note:
    If this register is not populated (mpu max freq field is 0), then we
    revert back to PG 2.0 OPP list.

    Signed-off-by: Hebbar Gururaja

    Hebbar Gururaja
     
  • ae25144ed   Revert "ARM: OMAP: AM33XX: Add OPP table for PG2.1 AM335x" ... Browse Code »

    This reverts commit ee9dfd8d729d3e7b5ce9e404a0e87f27f6f79135.

    This patch checks for the package type for checking the supported opp
    bits & also if the bits are set, the opp table is updated.
    However, checking package type bit is not required & also, the opp bit
    checking must be reversed.

    A fix for the same will follow after this commit

    Hebbar Gururaja