Eric Lee / smarc-uboot

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Commit d8fffa057c9430fd0c5104ab6ff7db4cdb03db51

Authored by Wolfgang Denk
2 parents 0dd78fb943 3c945542da
Exists in master and in 55 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Merge branch 'master' of git://git.denx.de/u-boot-mips 

* 'master' of git://git.denx.de/u-boot-mips:
  MIPS: Jz4740: Add qi_lb60 board support
  MIPS: Jz4740: Add NAND driver
  MIPS: Ingenic XBurst Jz4740 processor support

Showing 20 changed files Side-by-side Diff

... ... @@ -928,6 +928,10 @@
928 928  
929 929 vct_xxx MIPS32 4Kc
930 930  
  931 +Xiangfu Liu <xiangfu@openmobilefree.net>
  932 +
  933 + qi_lb60 MIPS32 (XBurst Jz4740 SoC)
  934 +
931 935 #########################################################################
932 936 # Nios-II Systems: #
933 937 # #
... ... @@ -400,7 +400,9 @@
400 400 ## MIPS Systems (little endian)
401 401 #########################################################################
402 402  
403   -LIST_mips4kc_el=""
  403 +LIST_mips4kc_el=" \
  404 + qi_lb60 \
  405 +"
404 406  
405 407 LIST_mips5kc_el=""
406 408  
... ... @@ -181,6 +181,7 @@
181 181 /mips Files generic to MIPS architecture
182 182 /cpu CPU specific files
183 183 /mips32 Files specific to MIPS32 CPUs
  184 + /xburst Files specific to Ingenic XBurst CPUs
184 185 /lib Architecture specific library files
185 186 /nios2 Files generic to Altera NIOS2 architecture
186 187 /cpu CPU specific files
arch/mips/cpu/xburst/Makefile
Diff comments   View file @ d8fffa0
  1 +#
  2 +# Copyright (C) 2011 Xiangfu Liu <xiangfu@openmobilefree.net>
  3 +#
  4 +# See file CREDITS for list of people who contributed to this
  5 +# project.
  6 +#
  7 +# This program is free software; you can redistribute it and/or
  8 +# modify it under the terms of the GNU General Public License as
  9 +# published by the Free Software Foundation; either version 2 of
  10 +# the License, or (at your option) any later version.
  11 +#
  12 +# This program is distributed in the hope that it will be useful,
  13 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15 +# GNU General Public License for more details.
  16 +#
  17 +# You should have received a copy of the GNU General Public License
  18 +# along with this program; if not, write to the Free Software
  19 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20 +# MA 02111-1307 USA
  21 +#
  22 +
  23 +include $(TOPDIR)/config.mk
  24 +
  25 +LIB = $(obj)lib$(CPU).o
  26 +
  27 +START = start.o
  28 +SOBJS-y =
  29 +COBJS-y = cpu.o timer.o jz_serial.o
  30 +
  31 +COBJS-$(CONFIG_JZ4740) += jz4740.o
  32 +
  33 +SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
  34 +OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
  35 +START := $(addprefix $(obj),$(START))
  36 +
  37 +all: $(obj).depend $(START) $(LIB)
  38 +
  39 +$(LIB): $(OBJS)
  40 + $(call cmd_link_o_target, $(OBJS))
  41 +
  42 +#########################################################################
  43 +
  44 +# defines $(obj).depend target
  45 +include $(SRCTREE)/rules.mk
  46 +
  47 +sinclude $(obj).depend
  48 +
  49 +#########################################################################
arch/mips/cpu/xburst/config.mk
Diff comments   View file @ d8fffa0
  1 +#
  2 +# Copyright (C) 2011 Xiangfu Liu <xiangfu@openmobilefree.net>
  3 +#
  4 +# See file CREDITS for list of people who contributed to this
  5 +# project.
  6 +#
  7 +# This program is free software; you can redistribute it and/or
  8 +# modify it under the terms of the GNU General Public License as
  9 +# published by the Free Software Foundation; either version 2 of
  10 +# the License, or (at your option) any later version.
  11 +#
  12 +# This program is distributed in the hope that it will be useful,
  13 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15 +# GNU General Public License for more details.
  16 +#
  17 +# You should have received a copy of the GNU General Public License
  18 +# along with this program; if not, write to the Free Software
  19 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20 +# MA 02111-1307 USA
  21 +#
  22 +
  23 +PLATFORM_CPPFLAGS += -march=mips32 -EL
  24 +PLATFORM_LDFLAGS += -EL
arch/mips/cpu/xburst/cpu.c
Diff comments   View file @ d8fffa0
  1 +/*
  2 + * (C) Copyright 2003
  3 + * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
  4 + * (C) Copyright 2011
  5 + * Xiangfu Liu <xiangfu@openmobilefree.net>
  6 + *
  7 + * See file CREDITS for list of people who contributed to this
  8 + * project.
  9 + *
  10 + * This program is free software; you can redistribute it and/or
  11 + * modify it under the terms of the GNU General Public License as
  12 + * published by the Free Software Foundation; either version 2 of
  13 + * the License, or (at your option) any later version.
  14 + *
  15 + * This program is distributed in the hope that it will be useful,
  16 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18 + * GNU General Public License for more details.
  19 + *
  20 + * You should have received a copy of the GNU General Public License
  21 + * along with this program; if not, write to the Free Software
  22 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23 + * MA 02111-1307 USA
  24 + */
  25 +
  26 +#include <common.h>
  27 +#include <command.h>
  28 +#include <netdev.h>
  29 +#include <asm/mipsregs.h>
  30 +#include <asm/cacheops.h>
  31 +#include <asm/reboot.h>
  32 +#include <asm/io.h>
  33 +#include <asm/jz4740.h>
  34 +
  35 +#define cache_op(op, addr) \
  36 + __asm__ __volatile__( \
  37 + ".set push\n" \
  38 + ".set noreorder\n" \
  39 + ".set mips3\n" \
  40 + "cache %0, %1\n" \
  41 + ".set pop\n" \
  42 + : \
  43 + : "i" (op), "R" (*(unsigned char *)(addr)))
  44 +
  45 +void __attribute__((weak)) _machine_restart(void)
  46 +{
  47 + struct jz4740_wdt *wdt = (struct jz4740_wdt *)JZ4740_WDT_BASE;
  48 + struct jz4740_tcu *tcu = (struct jz4740_tcu *)JZ4740_TCU_BASE;
  49 + u16 tmp;
  50 +
  51 + /* wdt_select_extalclk() */
  52 + tmp = readw(&wdt->tcsr);
  53 + tmp &= ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN);
  54 + tmp |= WDT_TCSR_EXT_EN;
  55 + writew(tmp, &wdt->tcsr);
  56 +
  57 + /* wdt_select_clk_div64() */
  58 + tmp = readw(&wdt->tcsr);
  59 + tmp &= ~WDT_TCSR_PRESCALE_MASK;
  60 + tmp |= WDT_TCSR_PRESCALE64,
  61 + writew(tmp, &wdt->tcsr);
  62 +
  63 + writew(100, &wdt->tdr); /* wdt_set_data(100) */
  64 + writew(0, &wdt->tcnt); /* wdt_set_count(0); */
  65 + writew(TCU_TSSR_WDTSC, &tcu->tscr); /* tcu_start_wdt_clock */
  66 + writeb(readb(&wdt->tcer) | WDT_TCER_TCEN, &wdt->tcer); /* wdt start */
  67 +
  68 + while (1)
  69 + ;
  70 +}
  71 +
  72 +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  73 +{
  74 + _machine_restart();
  75 +
  76 + fprintf(stderr, "*** reset failed ***\n");
  77 + return 0;
  78 +}
  79 +
  80 +void flush_cache(ulong start_addr, ulong size)
  81 +{
  82 + unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
  83 + unsigned long addr = start_addr & ~(lsize - 1);
  84 + unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
  85 +
  86 + for (; addr <= aend; addr += lsize) {
  87 + cache_op(Hit_Writeback_Inv_D, addr);
  88 + cache_op(Hit_Invalidate_I, addr);
  89 + }
  90 +}
  91 +
  92 +void flush_dcache_range(ulong start_addr, ulong stop)
  93 +{
  94 + unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
  95 + unsigned long addr = start_addr & ~(lsize - 1);
  96 + unsigned long aend = (stop - 1) & ~(lsize - 1);
  97 +
  98 + for (; addr <= aend; addr += lsize)
  99 + cache_op(Hit_Writeback_Inv_D, addr);
  100 +}
  101 +
  102 +void invalidate_dcache_range(ulong start_addr, ulong stop)
  103 +{
  104 + unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
  105 + unsigned long addr = start_addr & ~(lsize - 1);
  106 + unsigned long aend = (stop - 1) & ~(lsize - 1);
  107 +
  108 + for (; addr <= aend; addr += lsize)
  109 + cache_op(Hit_Invalidate_D, addr);
  110 +}
  111 +
  112 +void flush_icache_all(void)
  113 +{
  114 + u32 addr, t = 0;
  115 +
  116 + __asm__ __volatile__("mtc0 $0, $28"); /* Clear Taglo */
  117 + __asm__ __volatile__("mtc0 $0, $29"); /* Clear TagHi */
  118 +
  119 + for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_ICACHE_SIZE;
  120 + addr += CONFIG_SYS_CACHELINE_SIZE) {
  121 + cache_op(Index_Store_Tag_I, addr);
  122 + }
  123 +
  124 + /* invalidate btb */
  125 + __asm__ __volatile__(
  126 + ".set mips32\n\t"
  127 + "mfc0 %0, $16, 7\n\t"
  128 + "nop\n\t"
  129 + "ori %0,2\n\t"
  130 + "mtc0 %0, $16, 7\n\t"
  131 + ".set mips2\n\t"
  132 + :
  133 + : "r" (t));
  134 +}
  135 +
  136 +void flush_dcache_all(void)
  137 +{
  138 + u32 addr;
  139 +
  140 + for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE;
  141 + addr += CONFIG_SYS_CACHELINE_SIZE) {
  142 + cache_op(Index_Writeback_Inv_D, addr);
  143 + }
  144 +
  145 + __asm__ __volatile__("sync");
  146 +}
  147 +
  148 +void flush_cache_all(void)
  149 +{
  150 + flush_dcache_all();
  151 + flush_icache_all();
  152 +}
arch/mips/cpu/xburst/jz4740.c
Diff comments   View file @ d8fffa0
  1 +/*
  2 + * Jz4740 common routines
  3 + * Copyright (c) 2006 Ingenic Semiconductor, <jlwei@ingenic.cn>
  4 + *
  5 + * This program is free software; you can redistribute it and/or
  6 + * modify it under the terms of the GNU General Public License as
  7 + * published by the Free Software Foundation; either version 2 of
  8 + * the License, or (at your option) any later version.
  9 + *
  10 + * This program is distributed in the hope that it will be useful,
  11 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13 + * GNU General Public License for more details.
  14 + *
  15 + * You should have received a copy of the GNU General Public License
  16 + * along with this program; if not, write to the Free Software
  17 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18 + * MA 02111-1307 USA
  19 + */
  20 +
  21 +#include <config.h>
  22 +#include <common.h>
  23 +#include <asm/io.h>
  24 +#include <asm/jz4740.h>
  25 +
  26 +void enable_interrupts(void)
  27 +{
  28 +}
  29 +
  30 +int disable_interrupts(void)
  31 +{
  32 + return 0;
  33 +}
  34 +
  35 +/*
  36 + * PLL output clock = EXTAL * NF / (NR * NO)
  37 + * NF = FD + 2, NR = RD + 2
  38 + * NO = 1 (if OD = 0), NO = 2 (if OD = 1 or 2), NO = 4 (if OD = 3)
  39 + */
  40 +void pll_init(void)
  41 +{
  42 + struct jz4740_cpm *cpm = (struct jz4740_cpm *)JZ4740_CPM_BASE;
  43 +
  44 + register unsigned int cfcr, plcr1;
  45 + int n2FR[33] = {
  46 + 0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
  47 + 7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
  48 + 9
  49 + };
  50 + int div[5] = {1, 3, 3, 3, 3}; /* divisors of I:S:P:L:M */
  51 + int nf, pllout2;
  52 +
  53 + cfcr = CPM_CPCCR_CLKOEN |
  54 + CPM_CPCCR_PCS |
  55 + (n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) |
  56 + (n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) |
  57 + (n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) |
  58 + (n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) |
  59 + (n2FR[div[4]] << CPM_CPCCR_LDIV_BIT);
  60 +
  61 + pllout2 = (cfcr & CPM_CPCCR_PCS) ?
  62 + CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2);
  63 +
  64 + /* Init USB Host clock, pllout2 must be n*48MHz */
  65 + writel(pllout2 / 48000000 - 1, &cpm->uhccdr);
  66 +
  67 + nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL;
  68 + plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
  69 + (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
  70 + (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
  71 + (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
  72 + CPM_CPPCR_PLLEN; /* enable PLL */
  73 +
  74 + /* init PLL */
  75 + writel(cfcr, &cpm->cpccr);
  76 + writel(plcr1, &cpm->cppcr);
  77 +}
  78 +
  79 +void sdram_init(void)
  80 +{
  81 + struct jz4740_emc *emc = (struct jz4740_emc *)JZ4740_EMC_BASE;
  82 +
  83 + register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
  84 +
  85 + unsigned int cas_latency_sdmr[2] = {
  86 + EMC_SDMR_CAS_2,
  87 + EMC_SDMR_CAS_3,
  88 + };
  89 +
  90 + unsigned int cas_latency_dmcr[2] = {
  91 + 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */
  92 + 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */
  93 + };
  94 +
  95 + int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
  96 +
  97 + cpu_clk = CONFIG_SYS_CPU_SPEED;
  98 + mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
  99 +
  100 + writel(0, &emc->bcr); /* Disable bus release */
  101 + writew(0, &emc->rtcsr); /* Disable clock for counting */
  102 +
  103 + /* Fault DMCR value for mode register setting*/
  104 +#define SDRAM_ROW0 11
  105 +#define SDRAM_COL0 8
  106 +#define SDRAM_BANK40 0
  107 +
  108 + dmcr0 = ((SDRAM_ROW0 - 11) << EMC_DMCR_RA_BIT) |
  109 + ((SDRAM_COL0 - 8) << EMC_DMCR_CA_BIT) |
  110 + (SDRAM_BANK40 << EMC_DMCR_BA_BIT) |
  111 + (SDRAM_BW16 << EMC_DMCR_BW_BIT) |
  112 + EMC_DMCR_EPIN |
  113 + cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
  114 +
  115 + /* Basic DMCR value */
  116 + dmcr = ((SDRAM_ROW - 11) << EMC_DMCR_RA_BIT) |
  117 + ((SDRAM_COL - 8) << EMC_DMCR_CA_BIT) |
  118 + (SDRAM_BANK4 << EMC_DMCR_BA_BIT) |
  119 + (SDRAM_BW16 << EMC_DMCR_BW_BIT) |
  120 + EMC_DMCR_EPIN |
  121 + cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
  122 +
  123 + /* SDRAM timimg */
  124 + ns = 1000000000 / mem_clk;
  125 + tmp = SDRAM_TRAS / ns;
  126 + if (tmp < 4)
  127 + tmp = 4;
  128 + if (tmp > 11)
  129 + tmp = 11;
  130 + dmcr |= (tmp - 4) << EMC_DMCR_TRAS_BIT;
  131 + tmp = SDRAM_RCD / ns;
  132 +
  133 + if (tmp > 3)
  134 + tmp = 3;
  135 + dmcr |= tmp << EMC_DMCR_RCD_BIT;
  136 + tmp = SDRAM_TPC / ns;
  137 +
  138 + if (tmp > 7)
  139 + tmp = 7;
  140 + dmcr |= tmp << EMC_DMCR_TPC_BIT;
  141 + tmp = SDRAM_TRWL / ns;
  142 +
  143 + if (tmp > 3)
  144 + tmp = 3;
  145 + dmcr |= tmp << EMC_DMCR_TRWL_BIT;
  146 + tmp = (SDRAM_TRAS + SDRAM_TPC) / ns;
  147 +
  148 + if (tmp > 14)
  149 + tmp = 14;
  150 + dmcr |= ((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT;
  151 +
  152 + /* SDRAM mode value */
  153 + sdmode = EMC_SDMR_BT_SEQ |
  154 + EMC_SDMR_OM_NORMAL |
  155 + EMC_SDMR_BL_4 |
  156 + cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
  157 +
  158 + /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */
  159 + writel(dmcr, &emc->dmcr);
  160 + writeb(0, JZ4740_EMC_SDMR0 | sdmode);
  161 +
  162 + /* Wait for precharge, > 200us */
  163 + tmp = (cpu_clk / 1000000) * 1000;
  164 + while (tmp--)
  165 + ;
  166 +
  167 + /* Stage 2. Enable auto-refresh */
  168 + writel(dmcr | EMC_DMCR_RFSH, &emc->dmcr);
  169 +
  170 + tmp = SDRAM_TREF / ns;
  171 + tmp = tmp / 64 + 1;
  172 + if (tmp > 0xff)
  173 + tmp = 0xff;
  174 + writew(tmp, &emc->rtcor);
  175 + writew(0, &emc->rtcnt);
  176 + /* Divisor is 64, CKO/64 */
  177 + writew(EMC_RTCSR_CKS_64, &emc->rtcsr);
  178 +
  179 + /* Wait for number of auto-refresh cycles */
  180 + tmp = (cpu_clk / 1000000) * 1000;
  181 + while (tmp--)
  182 + ;
  183 +
  184 + /* Stage 3. Mode Register Set */
  185 + writel(dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET, &emc->dmcr);
  186 + writeb(0, JZ4740_EMC_SDMR0 | sdmode);
  187 +
  188 + /* Set back to basic DMCR value */
  189 + writel(dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET, &emc->dmcr);
  190 +
  191 + /* everything is ok now */
  192 +}
  193 +
  194 +DECLARE_GLOBAL_DATA_PTR;
  195 +
  196 +void calc_clocks(void)
  197 +{
  198 + unsigned int pllout;
  199 + unsigned int div[10] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
  200 +
  201 + pllout = __cpm_get_pllout();
  202 +
  203 + gd->cpu_clk = pllout / div[__cpm_get_cdiv()];
  204 + gd->sys_clk = pllout / div[__cpm_get_hdiv()];
  205 + gd->per_clk = pllout / div[__cpm_get_pdiv()];
  206 + gd->mem_clk = pllout / div[__cpm_get_mdiv()];
  207 + gd->dev_clk = CONFIG_SYS_EXTAL;
  208 +}
  209 +
  210 +void rtc_init(void)
  211 +{
  212 + struct jz4740_rtc *rtc = (struct jz4740_rtc *)JZ4740_RTC_BASE;
  213 +
  214 + while (!(readl(&rtc->rcr) & RTC_RCR_WRDY))
  215 + ;
  216 + writel(readl(&rtc->rcr) | RTC_RCR_AE, &rtc->rcr); /* enable alarm */
  217 +
  218 + while (!(readl(&rtc->rcr) & RTC_RCR_WRDY))
  219 + ;
  220 + writel(0x00007fff, &rtc->rgr); /* type value */
  221 +
  222 + while (!(readl(&rtc->rcr) & RTC_RCR_WRDY))
  223 + ;
  224 + writel(0x0000ffe0, &rtc->hwfcr); /* Power on delay 2s */
  225 +
  226 + while (!(readl(&rtc->rcr) & RTC_RCR_WRDY))
  227 + ;
  228 + writel(0x00000fe0, &rtc->hrcr); /* reset delay 125ms */
  229 +}
  230 +
  231 +/* U-Boot common routines */
  232 +phys_size_t initdram(int board_type)
  233 +{
  234 + struct jz4740_emc *emc = (struct jz4740_emc *)JZ4740_EMC_BASE;
  235 + u32 dmcr;
  236 + u32 rows, cols, dw, banks;
  237 + ulong size;
  238 +
  239 + dmcr = readl(&emc->dmcr);
  240 + rows = 11 + ((dmcr & EMC_DMCR_RA_MASK) >> EMC_DMCR_RA_BIT);
  241 + cols = 8 + ((dmcr & EMC_DMCR_CA_MASK) >> EMC_DMCR_CA_BIT);
  242 + dw = (dmcr & EMC_DMCR_BW) ? 2 : 4;
  243 + banks = (dmcr & EMC_DMCR_BA) ? 4 : 2;
  244 +
  245 + size = (1 << (rows + cols)) * dw * banks;
  246 +
  247 + return size;
  248 +}
arch/mips/cpu/xburst/jz_serial.c
Diff comments   View file @ d8fffa0
  1 +/*
  2 + * Jz4740 UART support
  3 + * Copyright (c) 2011
  4 + * Qi Hardware, Xiangfu Liu <xiangfu@sharism.cc>
  5 + *
  6 + * This program is free software; you can redistribute it and/or
  7 + * modify it under the terms of the GNU General Public License as
  8 + * published by the Free Software Foundation; either version 2 of
  9 + * the License, or (at your option) any later version.
  10 + *
  11 + * This program is distributed in the hope that it will be useful,
  12 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14 + * GNU General Public License for more details.
  15 + *
  16 + * You should have received a copy of the GNU General Public License
  17 + * along with this program; if not, write to the Free Software
  18 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19 + * MA 02111-1307 USA
  20 + */
  21 +
  22 +#include <config.h>
  23 +#include <common.h>
  24 +#include <asm/io.h>
  25 +#include <asm/jz4740.h>
  26 +
  27 +/*
  28 + * serial_init - initialize a channel
  29 + *
  30 + * This routine initializes the number of data bits, parity
  31 + * and set the selected baud rate. Interrupts are disabled.
  32 + * Set the modem control signals if the option is selected.
  33 + *
  34 + * RETURNS: N/A
  35 + */
  36 +struct jz4740_uart *uart = (struct jz4740_uart *)CONFIG_SYS_UART_BASE;
  37 +
  38 +int serial_init(void)
  39 +{
  40 + /* Disable port interrupts while changing hardware */
  41 + writeb(0, &uart->dlhr_ier);
  42 +
  43 + /* Disable UART unit function */
  44 + writeb(~UART_FCR_UUE, &uart->iir_fcr);
  45 +
  46 + /* Set both receiver and transmitter in UART mode (not SIR) */
  47 + writeb(~(SIRCR_RSIRE | SIRCR_TSIRE), &uart->isr);
  48 +
  49 + /*
  50 + * Set databits, stopbits and parity.
  51 + * (8-bit data, 1 stopbit, no parity)
  52 + */
  53 + writeb(UART_LCR_WLEN_8 | UART_LCR_STOP_1, &uart->lcr);
  54 +
  55 + /* Set baud rate */
  56 + serial_setbrg();
  57 +
  58 + /* Enable UART unit, enable and clear FIFO */
  59 + writeb(UART_FCR_UUE | UART_FCR_FE | UART_FCR_TFLS | UART_FCR_RFLS,
  60 + &uart->iir_fcr);
  61 +
  62 + return 0;
  63 +}
  64 +
  65 +void serial_setbrg(void)
  66 +{
  67 + u32 baud_div, tmp;
  68 +
  69 + baud_div = CONFIG_SYS_EXTAL / 16 / CONFIG_BAUDRATE;
  70 +
  71 + tmp = readb(&uart->lcr);
  72 + tmp |= UART_LCR_DLAB;
  73 + writeb(tmp, &uart->lcr);
  74 +
  75 + writeb((baud_div >> 8) & 0xff, &uart->dlhr_ier);
  76 + writeb(baud_div & 0xff, &uart->rbr_thr_dllr);
  77 +
  78 + tmp &= ~UART_LCR_DLAB;
  79 + writeb(tmp, &uart->lcr);
  80 +}
  81 +
  82 +int serial_tstc(void)
  83 +{
  84 + if (readb(&uart->lsr) & UART_LSR_DR)
  85 + return 1;
  86 +
  87 + return 0;
  88 +}
  89 +
  90 +void serial_putc(const char c)
  91 +{
  92 + if (c == '\n')
  93 + serial_putc('\r');
  94 +
  95 + /* Wait for fifo to shift out some bytes */
  96 + while (!((readb(&uart->lsr) & (UART_LSR_TDRQ | UART_LSR_TEMT)) == 0x60))
  97 + ;
  98 +
  99 + writeb((u8)c, &uart->rbr_thr_dllr);
  100 +}
  101 +
  102 +int serial_getc(void)
  103 +{
  104 + while (!serial_tstc())
  105 + ;
  106 +
  107 + return readb(&uart->rbr_thr_dllr);
  108 +}
  109 +
  110 +void serial_puts(const char *s)
  111 +{
  112 + while (*s)
  113 + serial_putc(*s++);
  114 +}
arch/mips/cpu/xburst/start.S
Diff comments   View file @ d8fffa0
  1 +/*
  2 + * Startup Code for MIPS32 XBURST CPU-core
  3 + *
  4 + * Copyright (c) 2010 Xiangfu Liu <xiangfu@sharism.cc>
  5 + *
  6 + * See file CREDITS for list of people who contributed to this
  7 + * project.
  8 + *
  9 + * This program is free software; you can redistribute it and/or
  10 + * modify it under the terms of the GNU General Public License as
  11 + * published by the Free Software Foundation; either version 2 of
  12 + * the License, or (at your option) any later version.
  13 + *
  14 + * This program is distributed in the hope that it will be useful,
  15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17 + * GNU General Public License for more details.
  18 + *
  19 + * You should have received a copy of the GNU General Public License
  20 + * along with this program; if not, write to the Free Software
  21 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 + * MA 02111-1307 USA
  23 + */
  24 +
  25 +#include <config.h>
  26 +#include <version.h>
  27 +#include <asm/regdef.h>
  28 +#include <asm/mipsregs.h>
  29 +#include <asm/addrspace.h>
  30 +#include <asm/cacheops.h>
  31 +
  32 + .set noreorder
  33 +
  34 + .globl _start
  35 + .text
  36 +_start:
  37 + /* Initialize $gp */
  38 + bal 1f
  39 + nop
  40 + .word _gp
  41 +1:
  42 + lw gp, 0(ra)
  43 +
  44 + /* Set up temporary stack */
  45 + li sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
  46 +
  47 + la t9, board_init_f
  48 + jr t9
  49 + nop
  50 +
  51 +/*
  52 + * void relocate_code (addr_sp, gd, addr_moni)
  53 + *
  54 + * This "function" does not return, instead it continues in RAM
  55 + * after relocating the monitor code.
  56 + *
  57 + * a0 = addr_sp
  58 + * a1 = gd
  59 + * a2 = destination address
  60 + */
  61 + .globl relocate_code
  62 + .ent relocate_code
  63 +relocate_code:
  64 + move sp, a0 # set new stack pointer
  65 +
  66 + li t0, CONFIG_SYS_MONITOR_BASE
  67 + la t3, in_ram
  68 + lw t2, -12(t3) # t2 <-- uboot_end_data
  69 + move t1, a2
  70 +
  71 + /*
  72 + * Fix $gp:
  73 + *
  74 + * New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination Address
  75 + */
  76 + move t6, gp
  77 + sub gp, CONFIG_SYS_MONITOR_BASE
  78 + add gp, a2 # gp now adjusted
  79 + sub t6, gp, t6 # t6 <-- relocation offset
  80 +
  81 + /*
  82 + * t0 = source address
  83 + * t1 = target address
  84 + * t2 = source end address
  85 + */
  86 +1:
  87 + lw t3, 0(t0)
  88 + sw t3, 0(t1)
  89 + addu t0, 4
  90 + ble t0, t2, 1b
  91 + addu t1, 4
  92 +
  93 + /* If caches were enabled, we would have to flush them here. */
  94 +
  95 + /* flush d-cache */
  96 + li t0, KSEG0
  97 + addi t1, t0, CONFIG_SYS_DCACHE_SIZE
  98 +2:
  99 + cache Index_Writeback_Inv_D, 0(t0)
  100 + bne t0, t1, 2b
  101 + addi t0, CONFIG_SYS_CACHELINE_SIZE
  102 +
  103 + sync
  104 +
  105 + /* flush i-cache */
  106 + li t0, KSEG0
  107 + addi t1, t0, CONFIG_SYS_ICACHE_SIZE
  108 +3:
  109 + cache Index_Invalidate_I, 0(t0)
  110 + bne t0, t1, 3b
  111 + addi t0, CONFIG_SYS_CACHELINE_SIZE
  112 +
  113 + /* Invalidate BTB */
  114 + mfc0 t0, CP0_CONFIG, 7
  115 + nop
  116 + ori t0, 2
  117 + mtc0 t0, CP0_CONFIG, 7
  118 + nop
  119 +
  120 + /* Jump to where we've relocated ourselves */
  121 + addi t0, a2, in_ram - _start
  122 + jr t0
  123 + nop
  124 +
  125 + .word _gp
  126 + .word _GLOBAL_OFFSET_TABLE_
  127 + .word uboot_end_data
  128 + .word uboot_end
  129 + .word num_got_entries
  130 +
  131 +in_ram:
  132 + /*
  133 + * Now we want to update GOT.
  134 + *
  135 + * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
  136 + * generated by GNU ld. Skip these reserved entries from relocation.
  137 + */
  138 + lw t3, -4(t0) # t3 <-- num_got_entries
  139 + lw t4, -16(t0) # t4 <-- _GLOBAL_OFFSET_TABLE_
  140 + lw t5, -20(t0) # t5 <-- _gp
  141 + sub t4, t5 # compute offset
  142 + add t4, t4, gp # t4 now holds relocated _G_O_T_
  143 + addi t4, t4, 8 # skipping first two entries
  144 + li t2, 2
  145 +1:
  146 + lw t1, 0(t4)
  147 + beqz t1, 2f
  148 + add t1, t6
  149 + sw t1, 0(t4)
  150 +2:
  151 + addi t2, 1
  152 + blt t2, t3, 1b
  153 + addi t4, 4
  154 +
  155 + /* Clear BSS */
  156 + lw t1, -12(t0) # t1 <-- uboot_end_data
  157 + lw t2, -8(t0) # t2 <-- uboot_end
  158 + add t1, t6 # adjust pointers
  159 + add t2, t6
  160 +
  161 + sub t1, 4
  162 +1: addi t1, 4
  163 + bltl t1, t2, 1b
  164 + sw zero, 0(t1)
  165 +
  166 + move a0, a1 # a0 <-- gd
  167 + la t9, board_init_r
  168 + jr t9
  169 + move a1, a2
  170 +
  171 + .end relocate_code
arch/mips/cpu/xburst/timer.c
Diff comments   View file @ d8fffa0
  1 +/*
  2 + * Copyright (c) 2006
  3 + * Ingenic Semiconductor, <jlwei@ingenic.cn>
  4 + *
  5 + * This program is free software; you can redistribute it and/or
  6 + * modify it under the terms of the GNU General Public License as
  7 + * published by the Free Software Foundation; either version 2 of
  8 + * the License, or (at your option) any later version.
  9 + *
  10 + * This program is distributed in the hope that it will be useful,
  11 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13 + * GNU General Public License for more details.
  14 + *
  15 + * You should have received a copy of the GNU General Public License
  16 + * along with this program; if not, write to the Free Software
  17 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18 + * MA 02111-1307 USA
  19 + */
  20 +
  21 +#include <config.h>
  22 +#include <common.h>
  23 +#include <asm/io.h>
  24 +
  25 +#include <asm/jz4740.h>
  26 +
  27 +#define TIMER_CHAN 0
  28 +#define TIMER_FDATA 0xffff /* Timer full data value */
  29 +
  30 +DECLARE_GLOBAL_DATA_PTR;
  31 +
  32 +static struct jz4740_tcu *tcu = (struct jz4740_tcu *)JZ4740_TCU_BASE;
  33 +
  34 +void reset_timer_masked(void)
  35 +{
  36 + /* reset time */
  37 + gd->lastinc = readw(&tcu->tcnt0);
  38 + gd->tbl = 0;
  39 +}
  40 +
  41 +ulong get_timer_masked(void)
  42 +{
  43 + ulong now = readw(&tcu->tcnt0);
  44 +
  45 + if (gd->lastinc <= now)
  46 + gd->tbl += now - gd->lastinc; /* normal mode */
  47 + else {
  48 + /* we have an overflow ... */
  49 + gd->tbl += TIMER_FDATA + now - gd->lastinc;
  50 + }
  51 +
  52 + gd->lastinc = now;
  53 +
  54 + return gd->tbl;
  55 +}
  56 +
  57 +void udelay_masked(unsigned long usec)
  58 +{
  59 + ulong tmo;
  60 + ulong endtime;
  61 + signed long diff;
  62 +
  63 + /* normalize */
  64 + if (usec >= 1000) {
  65 + tmo = usec / 1000;
  66 + tmo *= CONFIG_SYS_HZ;
  67 + tmo /= 1000;
  68 + } else {
  69 + if (usec > 1) {
  70 + tmo = usec * CONFIG_SYS_HZ;
  71 + tmo /= 1000*1000;
  72 + } else
  73 + tmo = 1;
  74 + }
  75 +
  76 + endtime = get_timer_masked() + tmo;
  77 +
  78 + do {
  79 + ulong now = get_timer_masked();
  80 + diff = endtime - now;
  81 + } while (diff >= 0);
  82 +}
  83 +
  84 +int timer_init(void)
  85 +{
  86 + writew(TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN, &tcu->tcsr0);
  87 +
  88 + writew(0, &tcu->tcnt0);
  89 + writew(0, &tcu->tdhr0);
  90 + writew(TIMER_FDATA, &tcu->tdfr0);
  91 +
  92 + /* mask irqs */
  93 + writel((1 << TIMER_CHAN) | (1 << (TIMER_CHAN + 16)), &tcu->tmsr);
  94 + writel(1 << TIMER_CHAN, &tcu->tscr); /* enable timer clock */
  95 + writeb(1 << TIMER_CHAN, &tcu->tesr); /* start counting up */
  96 +
  97 + gd->lastinc = 0;
  98 + gd->tbl = 0;
  99 +
  100 + return 0;
  101 +}
  102 +
  103 +void reset_timer(void)
  104 +{
  105 + reset_timer_masked();
  106 +}
  107 +
  108 +ulong get_timer(ulong base)
  109 +{
  110 + return get_timer_masked() - base;
  111 +}
  112 +
  113 +void set_timer(ulong t)
  114 +{
  115 + gd->tbl = t;
  116 +}
  117 +
  118 +void __udelay(unsigned long usec)
  119 +{
  120 + ulong tmo, tmp;
  121 +
  122 + /* normalize */
  123 + if (usec >= 1000) {
  124 + tmo = usec / 1000;
  125 + tmo *= CONFIG_SYS_HZ;
  126 + tmo /= 1000;
  127 + } else {
  128 + if (usec >= 1) {
  129 + tmo = usec * CONFIG_SYS_HZ;
  130 + tmo /= 1000 * 1000;
  131 + } else
  132 + tmo = 1;
  133 + }
  134 +
  135 + /* check for rollover during this delay */
  136 + tmp = get_timer(0);
  137 + if ((tmp + tmo) < tmp)
  138 + reset_timer_masked(); /* timer would roll over */
  139 + else
  140 + tmo += tmp;
  141 +
  142 + while (get_timer_masked() < tmo)
  143 + ;
  144 +}
  145 +
  146 +/*
  147 + * This function is derived from PowerPC code (read timebase as long long).
  148 + * On MIPS it just returns the timer value.
  149 + */
  150 +unsigned long long get_ticks(void)
  151 +{
  152 + return get_timer(0);
  153 +}
  154 +
  155 +/*
  156 + * This function is derived from PowerPC code (timebase clock frequency).
  157 + * On MIPS it returns the number of timer ticks per second.
  158 + */
  159 +ulong get_tbclk(void)
  160 +{
  161 + return CONFIG_SYS_HZ;
  162 +}
arch/mips/include/asm/global_data.h
Diff comments   View file @ d8fffa0
... ... @@ -39,6 +39,17 @@
39 39 typedef struct global_data {
40 40 bd_t *bd;
41 41 unsigned long flags;
  42 +#ifdef CONFIG_JZSOC
  43 + /* There are other clocks in the jz4740 */
  44 + unsigned long cpu_clk; /* CPU core clock */
  45 + unsigned long sys_clk; /* System bus clock */
  46 + unsigned long per_clk; /* Peripheral bus clock */
  47 + unsigned long mem_clk; /* Memory bus clock */
  48 + unsigned long dev_clk; /* Device clock */
  49 + /* "static data" needed by most of timer.c */
  50 + unsigned long tbl;
  51 + unsigned long lastinc;
  52 +#endif
42 53 unsigned long baudrate;
43 54 unsigned long have_console; /* serial_init() was called */
44 55 #ifdef CONFIG_PRE_CONSOLE_BUFFER
arch/mips/include/asm/jz4740.h
Diff comments   View file @ d8fffa0
Changes suppressed. Click to show
  1 +/*
  2 + * head file for Ingenic Semiconductor's JZ4740 CPU.
  3 + */
  4 +#ifndef __JZ4740_H__
  5 +#define __JZ4740_H__
  6 +
  7 +#include <asm/addrspace.h>
  8 +#include <asm/cacheops.h>
  9 +
  10 +/* Boot ROM Specification */
  11 +/* NOR Boot config */
  12 +#define JZ4740_NORBOOT_8BIT 0x00000000 /* 8-bit data bus flash */
  13 +#define JZ4740_NORBOOT_16BIT 0x10101010 /* 16-bit data bus flash */
  14 +#define JZ4740_NORBOOT_32BIT 0x20202020 /* 32-bit data bus flash */
  15 +/* NAND Boot config */
  16 +#define JZ4740_NANDBOOT_B8R3 0xffffffff /* 8-bit bus & 3 row cycles */
  17 +#define JZ4740_NANDBOOT_B8R2 0xf0f0f0f0 /* 8-bit bus & 2 row cycles */
  18 +#define JZ4740_NANDBOOT_B16R3 0x0f0f0f0f /* 16-bit bus & 3 row cycles */
  19 +#define JZ4740_NANDBOOT_B16R2 0x00000000 /* 16-bit bus & 2 row cycles */
  20 +
  21 +/* 1st-level interrupts */
  22 +#define JZ4740_IRQ_I2C 1
  23 +#define JZ4740_IRQ_UHC 3
  24 +#define JZ4740_IRQ_UART0 9
  25 +#define JZ4740_IRQ_SADC 12
  26 +#define JZ4740_IRQ_MSC 14
  27 +#define JZ4740_IRQ_RTC 15
  28 +#define JZ4740_IRQ_SSI 16
  29 +#define JZ4740_IRQ_CIM 17
  30 +#define JZ4740_IRQ_AIC 18
  31 +#define JZ4740_IRQ_ETH 19
  32 +#define JZ4740_IRQ_DMAC 20
  33 +#define JZ4740_IRQ_TCU2 21
  34 +#define JZ4740_IRQ_TCU1 22
  35 +#define JZ4740_IRQ_TCU0 23
  36 +#define JZ4740_IRQ_UDC 24
  37 +#define JZ4740_IRQ_GPIO3 25
  38 +#define JZ4740_IRQ_GPIO2 26
  39 +#define JZ4740_IRQ_GPIO1 27
  40 +#define JZ4740_IRQ_GPIO0 28
  41 +#define JZ4740_IRQ_IPU 29
  42 +#define JZ4740_IRQ_LCD 30
  43 +/* 2nd-level interrupts */
  44 +#define JZ4740_IRQ_DMA_0 32 /* 32 to 37 for DMAC channel 0 to 5 */
  45 +#define JZ4740_IRQ_GPIO_0 48 /* 48 to 175 for GPIO pin 0 to 127 */
  46 +
  47 +/* Register Definitions */
  48 +#define JZ4740_CPM_BASE 0x10000000
  49 +#define JZ4740_INTC_BASE 0x10001000
  50 +#define JZ4740_TCU_BASE 0x10002000
  51 +#define JZ4740_WDT_BASE 0x10002000
  52 +#define JZ4740_RTC_BASE 0x10003000
  53 +#define JZ4740_GPIO_BASE 0x10010000
  54 +#define JZ4740_AIC_BASE 0x10020000
  55 +#define JZ4740_ICDC_BASE 0x10020000
  56 +#define JZ4740_MSC_BASE 0x10021000
  57 +#define JZ4740_UART0_BASE 0x10030000
  58 +#define JZ4740_I2C_BASE 0x10042000
  59 +#define JZ4740_SSI_BASE 0x10043000
  60 +#define JZ4740_SADC_BASE 0x10070000
  61 +#define JZ4740_EMC_BASE 0x13010000
  62 +#define JZ4740_DMAC_BASE 0x13020000
  63 +#define JZ4740_UHC_BASE 0x13030000
  64 +#define JZ4740_UDC_BASE 0x13040000
  65 +#define JZ4740_LCD_BASE 0x13050000
  66 +#define JZ4740_SLCD_BASE 0x13050000
  67 +#define JZ4740_CIM_BASE 0x13060000
  68 +#define JZ4740_ETH_BASE 0x13100000
  69 +
  70 +/* 8bit Mode Register of SDRAM bank 0 */
  71 +#define JZ4740_EMC_SDMR0 (JZ4740_EMC_BASE + 0xa000)
  72 +
  73 +/* GPIO (General-Purpose I/O Ports) */
  74 +/* = 0,1,2,3 */
  75 +#define GPIO_PXPIN(n) \
  76 + (JZ4740_GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */
  77 +#define GPIO_PXDAT(n) \
  78 + (JZ4740_GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data Register */
  79 +#define GPIO_PXDATS(n) \
  80 + (JZ4740_GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */
  81 +#define GPIO_PXDATC(n) \
  82 + (JZ4740_GPIO_BASE + (0x18 + (n)*0x100)) /* Port Data Clear Register */
  83 +#define GPIO_PXIM(n) \
  84 + (JZ4740_GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt Mask Register */
  85 +#define GPIO_PXIMS(n) \
  86 + (JZ4740_GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt Mask Set Reg */
  87 +#define GPIO_PXIMC(n) \
  88 + (JZ4740_GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt Mask Clear Reg */
  89 +#define GPIO_PXPE(n) \
  90 + (JZ4740_GPIO_BASE + (0x30 + (n)*0x100)) /* Pull Enable Register */
  91 +#define GPIO_PXPES(n) \
  92 + (JZ4740_GPIO_BASE + (0x34 + (n)*0x100)) /* Pull Enable Set Reg. */
  93 +#define GPIO_PXPEC(n) \
  94 + (JZ4740_GPIO_BASE + (0x38 + (n)*0x100)) /* Pull Enable Clear Reg. */
  95 +#define GPIO_PXFUN(n) \
  96 + (JZ4740_GPIO_BASE + (0x40 + (n)*0x100)) /* Function Register */
  97 +#define GPIO_PXFUNS(n) \
  98 + (JZ4740_GPIO_BASE + (0x44 + (n)*0x100)) /* Function Set Register */
  99 +#define GPIO_PXFUNC(n) \
  100 + (JZ4740_GPIO_BASE + (0x48 + (n)*0x100)) /* Function Clear Register */
  101 +#define GPIO_PXSEL(n) \
  102 + (JZ4740_GPIO_BASE + (0x50 + (n)*0x100)) /* Select Register */
  103 +#define GPIO_PXSELS(n) \
  104 + (JZ4740_GPIO_BASE + (0x54 + (n)*0x100)) /* Select Set Register */
  105 +#define GPIO_PXSELC(n) \
  106 + (JZ4740_GPIO_BASE + (0x58 + (n)*0x100)) /* Select Clear Register */
  107 +#define GPIO_PXDIR(n) \
  108 + (JZ4740_GPIO_BASE + (0x60 + (n)*0x100)) /* Direction Register */
  109 +#define GPIO_PXDIRS(n) \
  110 + (JZ4740_GPIO_BASE + (0x64 + (n)*0x100)) /* Direction Set Register */
  111 +#define GPIO_PXDIRC(n) \
  112 + (JZ4740_GPIO_BASE + (0x68 + (n)*0x100)) /* Direction Clear Register */
  113 +#define GPIO_PXTRG(n) \
  114 + (JZ4740_GPIO_BASE + (0x70 + (n)*0x100)) /* Trigger Register */
  115 +#define GPIO_PXTRGS(n) \
  116 + (JZ4740_GPIO_BASE + (0x74 + (n)*0x100)) /* Trigger Set Register */
  117 +#define GPIO_PXTRGC(n) \
  118 + (JZ4740_GPIO_BASE + (0x78 + (n)*0x100)) /* Trigger Set Register */
  119 +
  120 +/* Static Memory Control Register */
  121 +#define EMC_SMCR_STRV_BIT 24
  122 +#define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT)
  123 +#define EMC_SMCR_TAW_BIT 20
  124 +#define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT)
  125 +#define EMC_SMCR_TBP_BIT 16
  126 +#define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT)
  127 +#define EMC_SMCR_TAH_BIT 12
  128 +#define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT)
  129 +#define EMC_SMCR_TAS_BIT 8
  130 +#define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT)
  131 +#define EMC_SMCR_BW_BIT 6
  132 +#define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT)
  133 + #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT)
  134 + #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT)
  135 + #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT)
  136 +#define EMC_SMCR_BCM (1 << 3)
  137 +#define EMC_SMCR_BL_BIT 1
  138 +#define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT)
  139 + #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT)
  140 + #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT)
  141 + #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT)
  142 + #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT)
  143 +#define EMC_SMCR_SMT (1 << 0)
  144 +
  145 +/* Static Memory Bank Addr Config Reg */
  146 +#define EMC_SACR_BASE_BIT 8
  147 +#define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT)
  148 +#define EMC_SACR_MASK_BIT 0
  149 +#define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT)
  150 +
  151 +/* NAND Flash Control/Status Register */
  152 +#define EMC_NFCSR_NFCE4 (1 << 7) /* NAND Flash Enable */
  153 +#define EMC_NFCSR_NFE4 (1 << 6) /* NAND Flash FCE# Assertion Enable */
  154 +#define EMC_NFCSR_NFCE3 (1 << 5)
  155 +#define EMC_NFCSR_NFE3 (1 << 4)
  156 +#define EMC_NFCSR_NFCE2 (1 << 3)
  157 +#define EMC_NFCSR_NFE2 (1 << 2)
  158 +#define EMC_NFCSR_NFCE1 (1 << 1)
  159 +#define EMC_NFCSR_NFE1 (1 << 0)
  160 +
  161 +/* NAND Flash ECC Control Register */
  162 +#define EMC_NFECR_PRDY (1 << 4) /* Parity Ready */
  163 +#define EMC_NFECR_RS_DECODING (0 << 3) /* RS is in decoding phase */
  164 +#define EMC_NFECR_RS_ENCODING (1 << 3) /* RS is in encoding phase */
  165 +#define EMC_NFECR_HAMMING (0 << 2) /* Use HAMMING Correction Algorithm */
  166 +#define EMC_NFECR_RS (1 << 2) /* Select RS Correction Algorithm */
  167 +#define EMC_NFECR_ERST (1 << 1) /* ECC Reset */
  168 +#define EMC_NFECR_ECCE (1 << 0) /* ECC Enable */
  169 +
  170 +/* NAND Flash ECC Data Register */
  171 +#define EMC_NFECC_ECC2_BIT 16
  172 +#define EMC_NFECC_ECC2_MASK (0xff << EMC_NFECC_ECC2_BIT)
  173 +#define EMC_NFECC_ECC1_BIT 8
  174 +#define EMC_NFECC_ECC1_MASK (0xff << EMC_NFECC_ECC1_BIT)
  175 +#define EMC_NFECC_ECC0_BIT 0
  176 +#define EMC_NFECC_ECC0_MASK (0xff << EMC_NFECC_ECC0_BIT)
  177 +
  178 +/* NAND Flash Interrupt Status Register */
  179 +#define EMC_NFINTS_ERRCNT_BIT 29 /* Error Count */
  180 +#define EMC_NFINTS_ERRCNT_MASK (0x7 << EMC_NFINTS_ERRCNT_BIT)
  181 +#define EMC_NFINTS_PADF (1 << 4) /* Padding Finished */
  182 +#define EMC_NFINTS_DECF (1 << 3) /* Decoding Finished */
  183 +#define EMC_NFINTS_ENCF (1 << 2) /* Encoding Finished */
  184 +#define EMC_NFINTS_UNCOR (1 << 1) /* Uncorrectable Error Occurred */
  185 +#define EMC_NFINTS_ERR (1 << 0) /* Error Occurred */
  186 +
  187 +/* NAND Flash Interrupt Enable Register */
  188 +#define EMC_NFINTE_PADFE (1 << 4) /* Padding Finished Interrupt */
  189 +#define EMC_NFINTE_DECFE (1 << 3) /* Decoding Finished Interrupt */
  190 +#define EMC_NFINTE_ENCFE (1 << 2) /* Encoding Finished Interrupt */
  191 +#define EMC_NFINTE_UNCORE (1 << 1) /* Uncorrectable Error Occurred Intr */
  192 +#define EMC_NFINTE_ERRE (1 << 0) /* Error Occurred Interrupt */
  193 +
  194 +/* NAND Flash RS Error Report Register */
  195 +#define EMC_NFERR_INDEX_BIT 16 /* Error Symbol Index */
  196 +#define EMC_NFERR_INDEX_MASK (0x1ff << EMC_NFERR_INDEX_BIT)
  197 +#define EMC_NFERR_MASK_BIT 0 /* Error Symbol Value */
  198 +#define EMC_NFERR_MASK_MASK (0x1ff << EMC_NFERR_MASK_BIT)
  199 +
  200 +/* DRAM Control Register */
  201 +#define EMC_DMCR_BW_BIT 31
  202 +#define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT)
  203 +#define EMC_DMCR_CA_BIT 26
  204 +#define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT)
  205 + #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT)
  206 + #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT)
  207 + #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT)
  208 + #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT)
  209 + #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT)
  210 +#define EMC_DMCR_RMODE (1 << 25)
  211 +#define EMC_DMCR_RFSH (1 << 24)
  212 +#define EMC_DMCR_MRSET (1 << 23)
  213 +#define EMC_DMCR_RA_BIT 20
  214 +#define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT)
  215 + #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT)
  216 + #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT)
  217 + #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT)
  218 +#define EMC_DMCR_BA_BIT 19
  219 +#define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT)
  220 +#define EMC_DMCR_PDM (1 << 18)
  221 +#define EMC_DMCR_EPIN (1 << 17)
  222 +#define EMC_DMCR_TRAS_BIT 13
  223 +#define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT)
  224 +#define EMC_DMCR_RCD_BIT 11
  225 +#define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT)
  226 +#define EMC_DMCR_TPC_BIT 8
  227 +#define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT)
  228 +#define EMC_DMCR_TRWL_BIT 5
  229 +#define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT)
  230 +#define EMC_DMCR_TRC_BIT 2
  231 +#define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT)
  232 +#define EMC_DMCR_TCL_BIT 0
  233 +#define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT)
  234 +
  235 +/* Refresh Time Control/Status Register */
  236 +#define EMC_RTCSR_CMF (1 << 7)
  237 +#define EMC_RTCSR_CKS_BIT 0
  238 +#define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT)
  239 + #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT)
  240 + #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT)
  241 + #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT)
  242 + #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT)
  243 + #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT)
  244 + #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT)
  245 + #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT)
  246 + #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT)
  247 +
  248 +/* SDRAM Bank Address Configuration Register */
  249 +#define EMC_DMAR_BASE_BIT 8
  250 +#define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT)
  251 +#define EMC_DMAR_MASK_BIT 0
  252 +#define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT)
  253 +
  254 +/* Mode Register of SDRAM bank 0 */
  255 +#define EMC_SDMR_BM (1 << 9) /* Write Burst Mode */
  256 +#define EMC_SDMR_OM_BIT 7 /* Operating Mode */
  257 +#define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT)
  258 + #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT)
  259 +#define EMC_SDMR_CAS_BIT 4 /* CAS Latency */
  260 +#define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT)
  261 + #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT)
  262 + #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT)
  263 + #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT)
  264 +#define EMC_SDMR_BT_BIT 3 /* Burst Type */
  265 +#define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT)
  266 + #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) /* Sequential */
  267 + #define EMC_SDMR_BT_INT (1 << EMC_SDMR_BT_BIT) /* Interleave */
  268 +#define EMC_SDMR_BL_BIT 0 /* Burst Length */
  269 +#define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT)
  270 + #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT)
  271 + #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT)
  272 + #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT)
  273 + #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT)
  274 +
  275 +#define EMC_SDMR_CAS2_16BIT \
  276 + (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
  277 +#define EMC_SDMR_CAS2_32BIT \
  278 + (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
  279 +#define EMC_SDMR_CAS3_16BIT \
  280 + (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
  281 +#define EMC_SDMR_CAS3_32BIT \
  282 + (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
  283 +
  284 +/* RTC Control Register */
  285 +#define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */
  286 +#define RTC_RCR_HZ (1 << 6) /* 1Hz Flag */
  287 +#define RTC_RCR_HZIE (1 << 5) /* 1Hz Interrupt Enable */
  288 +#define RTC_RCR_AF (1 << 4) /* Alarm Flag */
  289 +#define RTC_RCR_AIE (1 << 3) /* Alarm Interrupt Enable */
  290 +#define RTC_RCR_AE (1 << 2) /* Alarm Enable */
  291 +#define RTC_RCR_RTCE (1 << 0) /* RTC Enable */
  292 +
  293 +/* RTC Regulator Register */
  294 +#define RTC_RGR_LOCK (1 << 31) /* Lock Bit */
  295 +#define RTC_RGR_ADJC_BIT 16
  296 +#define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT)
  297 +#define RTC_RGR_NC1HZ_BIT 0
  298 +#define RTC_RGR_NC1HZ_MASK (0xffff << RTC_RGR_NC1HZ_BIT)
  299 +
  300 +/* Hibernate Control Register */
  301 +#define RTC_HCR_PD (1 << 0) /* Power Down */
  302 +
  303 +/* Hibernate Wakeup Filter Counter Register */
  304 +#define RTC_HWFCR_BIT 5
  305 +#define RTC_HWFCR_MASK (0x7ff << RTC_HWFCR_BIT)
  306 +
  307 +/* Hibernate Reset Counter Register */
  308 +#define RTC_HRCR_BIT 5
  309 +#define RTC_HRCR_MASK (0x7f << RTC_HRCR_BIT)
  310 +
  311 +/* Hibernate Wakeup Control Register */
  312 +#define RTC_HWCR_EALM (1 << 0) /* RTC alarm wakeup enable */
  313 +
  314 +/* Hibernate Wakeup Status Register */
  315 +#define RTC_HWRSR_HR (1 << 5) /* Hibernate reset */
  316 +#define RTC_HWRSR_PPR (1 << 4) /* PPR reset */
  317 +#define RTC_HWRSR_PIN (1 << 1) /* Wakeup pin status bit */
  318 +#define RTC_HWRSR_ALM (1 << 0) /* RTC alarm status bit */
  319 +
  320 +/* Clock Control Register */
  321 +#define CPM_CPCCR_I2CS (1 << 31)
  322 +#define CPM_CPCCR_CLKOEN (1 << 30)
  323 +#define CPM_CPCCR_UCS (1 << 29)
  324 +#define CPM_CPCCR_UDIV_BIT 23
  325 +#define CPM_CPCCR_UDIV_MASK (0x3f << CPM_CPCCR_UDIV_BIT)
  326 +#define CPM_CPCCR_CE (1 << 22)
  327 +#define CPM_CPCCR_PCS (1 << 21)
  328 +#define CPM_CPCCR_LDIV_BIT 16
  329 +#define CPM_CPCCR_LDIV_MASK (0x1f << CPM_CPCCR_LDIV_BIT)
  330 +#define CPM_CPCCR_MDIV_BIT 12
  331 +#define CPM_CPCCR_MDIV_MASK (0x0f << CPM_CPCCR_MDIV_BIT)
  332 +#define CPM_CPCCR_PDIV_BIT 8
  333 +#define CPM_CPCCR_PDIV_MASK (0x0f << CPM_CPCCR_PDIV_BIT)
  334 +#define CPM_CPCCR_HDIV_BIT 4
  335 +#define CPM_CPCCR_HDIV_MASK (0x0f << CPM_CPCCR_HDIV_BIT)
  336 +#define CPM_CPCCR_CDIV_BIT 0
  337 +#define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT)
  338 +
  339 +/* I2S Clock Divider Register */
  340 +#define CPM_I2SCDR_I2SDIV_BIT 0
  341 +#define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT)
  342 +
  343 +/* LCD Pixel Clock Divider Register */
  344 +#define CPM_LPCDR_PIXDIV_BIT 0
  345 +#define CPM_LPCDR_PIXDIV_MASK (0x1ff << CPM_LPCDR_PIXDIV_BIT)
  346 +
  347 +/* MSC Clock Divider Register */
  348 +#define CPM_MSCCDR_MSCDIV_BIT 0
  349 +#define CPM_MSCCDR_MSCDIV_MASK (0x1f << CPM_MSCCDR_MSCDIV_BIT)
  350 +
  351 +/* PLL Control Register */
  352 +#define CPM_CPPCR_PLLM_BIT 23
  353 +#define CPM_CPPCR_PLLM_MASK (0x1ff << CPM_CPPCR_PLLM_BIT)
  354 +#define CPM_CPPCR_PLLN_BIT 18
  355 +#define CPM_CPPCR_PLLN_MASK (0x1f << CPM_CPPCR_PLLN_BIT)
  356 +#define CPM_CPPCR_PLLOD_BIT 16
  357 +#define CPM_CPPCR_PLLOD_MASK (0x03 << CPM_CPPCR_PLLOD_BIT)
  358 +#define CPM_CPPCR_PLLS (1 << 10)
  359 +#define CPM_CPPCR_PLLBP (1 << 9)
  360 +#define CPM_CPPCR_PLLEN (1 << 8)
  361 +#define CPM_CPPCR_PLLST_BIT 0
  362 +#define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT)
  363 +
  364 +/* Low Power Control Register */
  365 +#define CPM_LCR_DOZE_DUTY_BIT 3
  366 +#define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT)
  367 +#define CPM_LCR_DOZE_ON (1 << 2)
  368 +#define CPM_LCR_LPM_BIT 0
  369 +#define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT)
  370 + #define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT)
  371 + #define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT)
  372 +
  373 +/* Clock Gate Register */
  374 +#define CPM_CLKGR_UART1 (1 << 15)
  375 +#define CPM_CLKGR_UHC (1 << 14)
  376 +#define CPM_CLKGR_IPU (1 << 13)
  377 +#define CPM_CLKGR_DMAC (1 << 12)
  378 +#define CPM_CLKGR_UDC (1 << 11)
  379 +#define CPM_CLKGR_LCD (1 << 10)
  380 +#define CPM_CLKGR_CIM (1 << 9)
  381 +#define CPM_CLKGR_SADC (1 << 8)
  382 +#define CPM_CLKGR_MSC (1 << 7)
  383 +#define CPM_CLKGR_AIC1 (1 << 6)
  384 +#define CPM_CLKGR_AIC2 (1 << 5)
  385 +#define CPM_CLKGR_SSI (1 << 4)
  386 +#define CPM_CLKGR_I2C (1 << 3)
  387 +#define CPM_CLKGR_RTC (1 << 2)
  388 +#define CPM_CLKGR_TCU (1 << 1)
  389 +#define CPM_CLKGR_UART0 (1 << 0)
  390 +
  391 +/* Sleep Control Register */
  392 +#define CPM_SCR_O1ST_BIT 8
  393 +#define CPM_SCR_O1ST_MASK (0xff << CPM_SCR_O1ST_BIT)
  394 +#define CPM_SCR_UDCPHY_ENABLE (1 << 6)
  395 +#define CPM_SCR_USBPHY_DISABLE (1 << 7)
  396 +#define CPM_SCR_OSC_ENABLE (1 << 4)
  397 +
  398 +/* Hibernate Control Register */
  399 +#define CPM_HCR_PD (1 << 0)
  400 +
  401 +/* Wakeup Filter Counter Register in Hibernate Mode */
  402 +#define CPM_HWFCR_TIME_BIT 0
  403 +#define CPM_HWFCR_TIME_MASK (0x3ff << CPM_HWFCR_TIME_BIT)
  404 +
  405 +/* Reset Counter Register in Hibernate Mode */
  406 +#define CPM_HRCR_TIME_BIT 0
  407 +#define CPM_HRCR_TIME_MASK (0x7f << CPM_HRCR_TIME_BIT)
  408 +
  409 +/* Wakeup Control Register in Hibernate Mode */
  410 +#define CPM_HWCR_WLE_LOW (0 << 2)
  411 +#define CPM_HWCR_WLE_HIGH (1 << 2)
  412 +#define CPM_HWCR_PIN_WAKEUP (1 << 1)
  413 +#define CPM_HWCR_RTC_WAKEUP (1 << 0)
  414 +
  415 +/* Wakeup Status Register in Hibernate Mode */
  416 +#define CPM_HWSR_WSR_PIN (1 << 1)
  417 +#define CPM_HWSR_WSR_RTC (1 << 0)
  418 +
  419 +/* Reset Status Register */
  420 +#define CPM_RSR_HR (1 << 2)
  421 +#define CPM_RSR_WR (1 << 1)
  422 +#define CPM_RSR_PR (1 << 0)
  423 +
  424 +/* Register definitions */
  425 +#define TCU_TCSR_PWM_SD (1 << 9)
  426 +#define TCU_TCSR_PWM_INITL_HIGH (1 << 8)
  427 +#define TCU_TCSR_PWM_EN (1 << 7)
  428 +#define TCU_TCSR_PRESCALE_BIT 3
  429 +#define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT)
  430 +#define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT)
  431 +#define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT)
  432 +#define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT)
  433 +#define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT)
  434 +#define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT)
  435 +#define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT)
  436 +#define TCU_TCSR_EXT_EN (1 << 2)
  437 +#define TCU_TCSR_RTC_EN (1 << 1)
  438 +#define TCU_TCSR_PCK_EN (1 << 0)
  439 +
  440 +#define TCU_TER_TCEN5 (1 << 5)
  441 +#define TCU_TER_TCEN4 (1 << 4)
  442 +#define TCU_TER_TCEN3 (1 << 3)
  443 +#define TCU_TER_TCEN2 (1 << 2)
  444 +#define TCU_TER_TCEN1 (1 << 1)
  445 +#define TCU_TER_TCEN0 (1 << 0)
  446 +
  447 +#define TCU_TESR_TCST5 (1 << 5)
  448 +#define TCU_TESR_TCST4 (1 << 4)
  449 +#define TCU_TESR_TCST3 (1 << 3)
  450 +#define TCU_TESR_TCST2 (1 << 2)
  451 +#define TCU_TESR_TCST1 (1 << 1)
  452 +#define TCU_TESR_TCST0 (1 << 0)
  453 +
  454 +#define TCU_TECR_TCCL5 (1 << 5)
  455 +#define TCU_TECR_TCCL4 (1 << 4)
  456 +#define TCU_TECR_TCCL3 (1 << 3)
  457 +#define TCU_TECR_TCCL2 (1 << 2)
  458 +#define TCU_TECR_TCCL1 (1 << 1)
  459 +#define TCU_TECR_TCCL0 (1 << 0)
  460 +
  461 +#define TCU_TFR_HFLAG5 (1 << 21)
  462 +#define TCU_TFR_HFLAG4 (1 << 20)
  463 +#define TCU_TFR_HFLAG3 (1 << 19)
  464 +#define TCU_TFR_HFLAG2 (1 << 18)
  465 +#define TCU_TFR_HFLAG1 (1 << 17)
  466 +#define TCU_TFR_HFLAG0 (1 << 16)
  467 +#define TCU_TFR_FFLAG5 (1 << 5)
  468 +#define TCU_TFR_FFLAG4 (1 << 4)
  469 +#define TCU_TFR_FFLAG3 (1 << 3)
  470 +#define TCU_TFR_FFLAG2 (1 << 2)
  471 +#define TCU_TFR_FFLAG1 (1 << 1)
  472 +#define TCU_TFR_FFLAG0 (1 << 0)
  473 +
  474 +#define TCU_TFSR_HFLAG5 (1 << 21)
  475 +#define TCU_TFSR_HFLAG4 (1 << 20)
  476 +#define TCU_TFSR_HFLAG3 (1 << 19)
  477 +#define TCU_TFSR_HFLAG2 (1 << 18)
  478 +#define TCU_TFSR_HFLAG1 (1 << 17)
  479 +#define TCU_TFSR_HFLAG0 (1 << 16)
  480 +#define TCU_TFSR_FFLAG5 (1 << 5)
  481 +#define TCU_TFSR_FFLAG4 (1 << 4)
  482 +#define TCU_TFSR_FFLAG3 (1 << 3)
  483 +#define TCU_TFSR_FFLAG2 (1 << 2)
  484 +#define TCU_TFSR_FFLAG1 (1 << 1)
  485 +#define TCU_TFSR_FFLAG0 (1 << 0)
  486 +
  487 +#define TCU_TFCR_HFLAG5 (1 << 21)
  488 +#define TCU_TFCR_HFLAG4 (1 << 20)
  489 +#define TCU_TFCR_HFLAG3 (1 << 19)
  490 +#define TCU_TFCR_HFLAG2 (1 << 18)
  491 +#define TCU_TFCR_HFLAG1 (1 << 17)
  492 +#define TCU_TFCR_HFLAG0 (1 << 16)
  493 +#define TCU_TFCR_FFLAG5 (1 << 5)
  494 +#define TCU_TFCR_FFLAG4 (1 << 4)
  495 +#define TCU_TFCR_FFLAG3 (1 << 3)
  496 +#define TCU_TFCR_FFLAG2 (1 << 2)
  497 +#define TCU_TFCR_FFLAG1 (1 << 1)
  498 +#define TCU_TFCR_FFLAG0 (1 << 0)
  499 +
  500 +#define TCU_TMR_HMASK5 (1 << 21)
  501 +#define TCU_TMR_HMASK4 (1 << 20)
  502 +#define TCU_TMR_HMASK3 (1 << 19)
  503 +#define TCU_TMR_HMASK2 (1 << 18)
  504 +#define TCU_TMR_HMASK1 (1 << 17)
  505 +#define TCU_TMR_HMASK0 (1 << 16)
  506 +#define TCU_TMR_FMASK5 (1 << 5)
  507 +#define TCU_TMR_FMASK4 (1 << 4)
  508 +#define TCU_TMR_FMASK3 (1 << 3)
  509 +#define TCU_TMR_FMASK2 (1 << 2)
  510 +#define TCU_TMR_FMASK1 (1 << 1)
  511 +#define TCU_TMR_FMASK0 (1 << 0)
  512 +
  513 +#define TCU_TMSR_HMST5 (1 << 21)
  514 +#define TCU_TMSR_HMST4 (1 << 20)
  515 +#define TCU_TMSR_HMST3 (1 << 19)
  516 +#define TCU_TMSR_HMST2 (1 << 18)
  517 +#define TCU_TMSR_HMST1 (1 << 17)
  518 +#define TCU_TMSR_HMST0 (1 << 16)
  519 +#define TCU_TMSR_FMST5 (1 << 5)
  520 +#define TCU_TMSR_FMST4 (1 << 4)
  521 +#define TCU_TMSR_FMST3 (1 << 3)
  522 +#define TCU_TMSR_FMST2 (1 << 2)
  523 +#define TCU_TMSR_FMST1 (1 << 1)
  524 +#define TCU_TMSR_FMST0 (1 << 0)
  525 +
  526 +#define TCU_TMCR_HMCL5 (1 << 21)
  527 +#define TCU_TMCR_HMCL4 (1 << 20)
  528 +#define TCU_TMCR_HMCL3 (1 << 19)
  529 +#define TCU_TMCR_HMCL2 (1 << 18)
  530 +#define TCU_TMCR_HMCL1 (1 << 17)
  531 +#define TCU_TMCR_HMCL0 (1 << 16)
  532 +#define TCU_TMCR_FMCL5 (1 << 5)
  533 +#define TCU_TMCR_FMCL4 (1 << 4)
  534 +#define TCU_TMCR_FMCL3 (1 << 3)
  535 +#define TCU_TMCR_FMCL2 (1 << 2)
  536 +#define TCU_TMCR_FMCL1 (1 << 1)
  537 +#define TCU_TMCR_FMCL0 (1 << 0)
  538 +
  539 +#define TCU_TSR_WDTS (1 << 16)
  540 +#define TCU_TSR_STOP5 (1 << 5)
  541 +#define TCU_TSR_STOP4 (1 << 4)
  542 +#define TCU_TSR_STOP3 (1 << 3)
  543 +#define TCU_TSR_STOP2 (1 << 2)
  544 +#define TCU_TSR_STOP1 (1 << 1)
  545 +#define TCU_TSR_STOP0 (1 << 0)
  546 +
  547 +#define TCU_TSSR_WDTSS (1 << 16)
  548 +#define TCU_TSSR_STPS5 (1 << 5)
  549 +#define TCU_TSSR_STPS4 (1 << 4)
  550 +#define TCU_TSSR_STPS3 (1 << 3)
  551 +#define TCU_TSSR_STPS2 (1 << 2)
  552 +#define TCU_TSSR_STPS1 (1 << 1)
  553 +#define TCU_TSSR_STPS0 (1 << 0)
  554 +
  555 +#define TCU_TSSR_WDTSC (1 << 16)
  556 +#define TCU_TSSR_STPC5 (1 << 5)
  557 +#define TCU_TSSR_STPC4 (1 << 4)
  558 +#define TCU_TSSR_STPC3 (1 << 3)
  559 +#define TCU_TSSR_STPC2 (1 << 2)
  560 +#define TCU_TSSR_STPC1 (1 << 1)
  561 +#define TCU_TSSR_STPC0 (1 << 0)
  562 +
  563 +/* Register definition */
  564 +#define WDT_TCSR_PRESCALE_BIT 3
  565 +#define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT)
  566 + #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT)
  567 + #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT)
  568 + #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT)
  569 + #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT)
  570 + #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT)
  571 + #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT)
  572 +#define WDT_TCSR_EXT_EN (1 << 2)
  573 +#define WDT_TCSR_RTC_EN (1 << 1)
  574 +#define WDT_TCSR_PCK_EN (1 << 0)
  575 +#define WDT_TCER_TCEN (1 << 0)
  576 +
  577 +/*
  578 + * Define macros for UART_IER
  579 + * UART Interrupt Enable Register
  580 + */
  581 +#define UART_IER_RIE (1 << 0) /* 0: receive fifo full interrupt disable */
  582 +#define UART_IER_TIE (1 << 1) /* 0: transmit fifo empty interrupt disable */
  583 +#define UART_IER_RLIE (1 << 2) /* 0: receive line status interrupt disable */
  584 +#define UART_IER_MIE (1 << 3) /* 0: modem status interrupt disable */
  585 +#define UART_IER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */
  586 +
  587 +/*
  588 + * Define macros for UART_ISR
  589 + * UART Interrupt Status Register
  590 + */
  591 +#define UART_ISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */
  592 +#define UART_ISR_IID (7 << 1) /* Source of Interrupt */
  593 +#define UART_ISR_IID_MSI (0 << 1) /* Modem status interrupt */
  594 +#define UART_ISR_IID_THRI (1 << 1) /* Transmitter holding register empty */
  595 +#define UART_ISR_IID_RDI (2 << 1) /* Receiver data interrupt */
  596 +#define UART_ISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */
  597 +/* FIFO mode select, set when UART_FCR.FE is set to 1 */
  598 +#define UART_ISR_FFMS (3 << 6)
  599 +#define UART_ISR_FFMS_NO_FIFO (0 << 6)
  600 +#define UART_ISR_FFMS_FIFO_MODE (3 << 6)
  601 +
  602 +/*
  603 + * Define macros for UART_FCR
  604 + * UART FIFO Control Register
  605 + */
  606 +#define UART_FCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */
  607 +#define UART_FCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */
  608 +#define UART_FCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */
  609 +#define UART_FCR_DMS (1 << 3) /* 0: disable DMA mode */
  610 +#define UART_FCR_UUE (1 << 4) /* 0: disable UART */
  611 +#define UART_FCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */
  612 +#define UART_FCR_RTRG_1 (0 << 6)
  613 +#define UART_FCR_RTRG_4 (1 << 6)
  614 +#define UART_FCR_RTRG_8 (2 << 6)
  615 +#define UART_FCR_RTRG_15 (3 << 6)
  616 +
  617 +/*
  618 + * Define macros for UART_LCR
  619 + * UART Line Control Register
  620 + */
  621 +#define UART_LCR_WLEN (3 << 0) /* word length */
  622 +#define UART_LCR_WLEN_5 (0 << 0)
  623 +#define UART_LCR_WLEN_6 (1 << 0)
  624 +#define UART_LCR_WLEN_7 (2 << 0)
  625 +#define UART_LCR_WLEN_8 (3 << 0)
  626 +#define UART_LCR_STOP (1 << 2)
  627 + /* 0: 1 stop bit when word length is 5,6,7,8
  628 + 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
  629 +#define UART_LCR_STOP_1 (0 << 2)
  630 + /* 0: 1 stop bit when word length is 5,6,7,8
  631 + 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
  632 +#define UART_LCR_STOP_2 (1 << 2)
  633 + /* 0: 1 stop bit when word length is 5,6,7,8
  634 + 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
  635 +
  636 +#define UART_LCR_PE (1 << 3) /* 0: parity disable */
  637 +#define UART_LCR_PROE (1 << 4) /* 0: even parity 1: odd parity */
  638 +#define UART_LCR_SPAR (1 << 5) /* 0: sticky parity disable */
  639 +#define UART_LCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */
  640 +/* 0: access UART_RDR/TDR/IER 1: access UART_DLLR/DLHR */
  641 +#define UART_LCR_DLAB (1 << 7)
  642 +
  643 +/*
  644 + * Define macros for UART_LSR
  645 + * UART Line Status Register
  646 + */
  647 +/* 0: receive FIFO is empty 1: receive data is ready */
  648 +#define UART_LSR_DR (1 << 0)
  649 +/* 0: no overrun error */
  650 +#define UART_LSR_ORER (1 << 1)
  651 +/* 0: no parity error */
  652 +#define UART_LSR_PER (1 << 2)
  653 +/* 0; no framing error */
  654 +#define UART_LSR_FER (1 << 3)
  655 +/* 0: no break detected 1: receive a break signal */
  656 +#define UART_LSR_BRK (1 << 4)
  657 +/* 1: transmit FIFO half "empty" */
  658 +#define UART_LSR_TDRQ (1 << 5)
  659 +/* 1: transmit FIFO and shift registers empty */
  660 +#define UART_LSR_TEMT (1 << 6)
  661 +/* 0: no receive error 1: receive error in FIFO mode */
  662 +#define UART_LSR_RFER (1 << 7)
  663 +
  664 +/*
  665 + * Define macros for UART_MCR
  666 + * UART Modem Control Register
  667 + */
  668 +#define UART_MCR_DTR (1 << 0) /* 0: DTR_ ouput high */
  669 +#define UART_MCR_RTS (1 << 1) /* 0: RTS_ output high */
  670 +/* 0: UART_MSR.RI is set to 0 and RI_ input high */
  671 +#define UART_MCR_OUT1 (1 << 2)
  672 +/* 0: UART_MSR.DCD is set to 0 and DCD_ input high */
  673 +#define UART_MCR_OUT2 (1 << 3)
  674 +#define UART_MCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */
  675 +#define UART_MCR_MCE (1 << 7) /* 0: modem function is disable */
  676 +
  677 +/*
  678 + * Define macros for UART_MSR
  679 + * UART Modem Status Register
  680 + */
  681 +#define UART_MSR_DCTS (1 << 0) /* 0: no change on CTS_ since last read */
  682 +#define UART_MSR_DDSR (1 << 1) /* 0: no change on DSR_ since last read */
  683 +#define UART_MSR_DRI (1 << 2) /* 0: no change on RI_ since last read */
  684 +#define UART_MSR_DDCD (1 << 3) /* 0: no change on DCD_ since last read */
  685 +#define UART_MSR_CTS (1 << 4) /* 0: CTS_ pin is high */
  686 +#define UART_MSR_DSR (1 << 5) /* 0: DSR_ pin is high */
  687 +#define UART_MSR_RI (1 << 6) /* 0: RI_ pin is high */
  688 +#define UART_MSR_DCD (1 << 7) /* 0: DCD_ pin is high */
  689 +
  690 +/*
  691 + * Define macros for SIRCR
  692 + * Slow IrDA Control Register
  693 + */
  694 +#define SIRCR_TSIRE (1 << 0) /* 0: TX is in UART mode 1: IrDA mode */
  695 +#define SIRCR_RSIRE (1 << 1) /* 0: RX is in UART mode 1: IrDA mode */
  696 +#define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length
  697 + 1: 0 pulse width is 1.6us for 115.2Kbps */
  698 +#define SIRCR_TXPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */
  699 +#define SIRCR_RXPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */
  700 +
  701 +/* MSC Clock and Control Register (MSC_STRPCL) */
  702 +#define MSC_STRPCL_EXIT_MULTIPLE (1 << 7)
  703 +#define MSC_STRPCL_EXIT_TRANSFER (1 << 6)
  704 +#define MSC_STRPCL_START_READWAIT (1 << 5)
  705 +#define MSC_STRPCL_STOP_READWAIT (1 << 4)
  706 +#define MSC_STRPCL_RESET (1 << 3)
  707 +#define MSC_STRPCL_START_OP (1 << 2)
  708 +#define MSC_STRPCL_CLOCK_CONTROL_BIT 0
  709 +#define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT)
  710 +#define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT)
  711 +#define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT)
  712 +
  713 +/* MSC Status Register (MSC_STAT) */
  714 +#define MSC_STAT_IS_RESETTING (1 << 15)
  715 +#define MSC_STAT_SDIO_INT_ACTIVE (1 << 14)
  716 +#define MSC_STAT_PRG_DONE (1 << 13)
  717 +#define MSC_STAT_DATA_TRAN_DONE (1 << 12)
  718 +#define MSC_STAT_END_CMD_RES (1 << 11)
  719 +#define MSC_STAT_DATA_FIFO_AFULL (1 << 10)
  720 +#define MSC_STAT_IS_READWAIT (1 << 9)
  721 +#define MSC_STAT_CLK_EN (1 << 8)
  722 +#define MSC_STAT_DATA_FIFO_FULL (1 << 7)
  723 +#define MSC_STAT_DATA_FIFO_EMPTY (1 << 6)
  724 +#define MSC_STAT_CRC_RES_ERR (1 << 5)
  725 +#define MSC_STAT_CRC_READ_ERROR (1 << 4)
  726 +#define MSC_STAT_CRC_WRITE_ERROR_BIT 2
  727 +#define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT)
  728 +/* No error on transmission of data */
  729 + #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT)
  730 +/* Card observed erroneous transmission of data */
  731 + #define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT)
  732 +/* No CRC status is sent back */
  733 + #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT)
  734 +#define MSC_STAT_TIME_OUT_RES (1 << 1)
  735 +#define MSC_STAT_TIME_OUT_READ (1 << 0)
  736 +
  737 +/* MSC Bus Clock Control Register (MSC_CLKRT) */
  738 +#define MSC_CLKRT_CLK_RATE_BIT 0
  739 +#define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT)
  740 + #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT)
  741 + #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT)
  742 + #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT)
  743 + #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT)
  744 + #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT)
  745 + #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT)
  746 + #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT)
  747 + #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT)
  748 +
  749 +/* MSC Command Sequence Control Register (MSC_CMDAT) */
  750 +#define MSC_CMDAT_IO_ABORT (1 << 11)
  751 +#define MSC_CMDAT_BUS_WIDTH_BIT 9
  752 +#define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT)
  753 +#define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT)
  754 +#define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT)
  755 +#define MSC_CMDAT_DMA_EN (1 << 8)
  756 +#define MSC_CMDAT_INIT (1 << 7)
  757 +#define MSC_CMDAT_BUSY (1 << 6)
  758 +#define MSC_CMDAT_STREAM_BLOCK (1 << 5)
  759 +#define MSC_CMDAT_WRITE (1 << 4)
  760 +#define MSC_CMDAT_READ (0 << 4)
  761 +#define MSC_CMDAT_DATA_EN (1 << 3)
  762 +#define MSC_CMDAT_RESPONSE_BIT 0
  763 +#define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT)
  764 +#define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT)
  765 +#define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT)
  766 +#define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT)
  767 +#define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT)
  768 +#define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT)
  769 +#define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT)
  770 +#define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT)
  771 +
  772 +/* MSC Interrupts Mask Register (MSC_IMASK) */
  773 +#define MSC_IMASK_SDIO (1 << 7)
  774 +#define MSC_IMASK_TXFIFO_WR_REQ (1 << 6)
  775 +#define MSC_IMASK_RXFIFO_RD_REQ (1 << 5)
  776 +#define MSC_IMASK_END_CMD_RES (1 << 2)
  777 +#define MSC_IMASK_PRG_DONE (1 << 1)
  778 +#define MSC_IMASK_DATA_TRAN_DONE (1 << 0)
  779 +
  780 +#ifndef __ASSEMBLY__
  781 +/* INTC (Interrupt Controller) */
  782 +struct jz4740_intc {
  783 + uint32_t isr; /* interrupt source register */
  784 + uint32_t imr; /* interrupt mask register */
  785 + uint32_t imsr; /* interrupt mask set register */
  786 + uint32_t imcr; /* interrupt mask clear register */
  787 + uint32_t ipr; /* interrupt pending register */
  788 +};
  789 +
  790 +/* RTC */
  791 +struct jz4740_rtc {
  792 + uint32_t rcr; /* rtc control register */
  793 + uint32_t rsr; /* rtc second register */
  794 + uint32_t rsar; /* rtc second alarm register */
  795 + uint32_t rgr; /* rtc regulator register */
  796 + uint32_t hcr; /* hibernate control register */
  797 + uint32_t hwfcr; /* hibernate wakeup filter counter reg */
  798 + uint32_t hrcr; /* hibernate reset counter reg */
  799 + uint32_t hwcr; /* hibernate wakeup control register */
  800 + uint32_t hwrsr; /* hibernate wakeup status reg */
  801 + uint32_t hspr; /* scratch pattern register */
  802 +};
  803 +
  804 +/* CPM (Clock reset and Power control Management) */
  805 +struct jz4740_cpm {
  806 + uint32_t cpccr; /* 0x00 clock control reg */
  807 + uint32_t lcr; /* 0x04 low power control reg */
  808 + uint32_t rsr; /* 0x08 reset status reg */
  809 + uint32_t pad00;
  810 + uint32_t cppcr; /* 0x10 pll control reg */
  811 + uint32_t pad01[3];
  812 + uint32_t clkgr; /* 0x20 clock gate reg */
  813 + uint32_t scr; /* 0x24 sleep control reg */
  814 + uint32_t pad02[14];
  815 + uint32_t i2scd; /* 0x60 I2S device clock divider reg */
  816 + uint32_t lpcdr; /* 0x64 LCD pix clock divider reg */
  817 + uint32_t msccdr; /* 0x68 MSC device clock divider reg */
  818 + uint32_t uhccdr; /* 0x6C UHC 48M clock divider reg */
  819 + uint32_t uhcts; /* 0x70 UHC PHY test point reg */
  820 + uint32_t ssicd; /* 0x74 SSI clock divider reg */
  821 +};
  822 +
  823 +/* TCU (Timer Counter Unit) */
  824 +struct jz4740_tcu {
  825 + uint32_t pad00[4];
  826 + uint32_t ter; /* 0x10 Timer Counter Enable Register */
  827 + uint32_t tesr; /* 0x14 Timer Counter Enable Set Register */
  828 + uint32_t tecr; /* 0x18 Timer Counter Enable Clear Register */
  829 + uint32_t tsr; /* 0x1C Timer Stop Register */
  830 + uint32_t tfr; /* 0x20 Timer Flag Register */
  831 + uint32_t tfsr; /* 0x24 Timer Flag Set Register */
  832 + uint32_t tfcr; /* 0x28 Timer Flag Clear Register */
  833 + uint32_t tssr; /* 0x2C Timer Stop Set Register */
  834 + uint32_t tmr; /* 0x30 Timer Mask Register */
  835 + uint32_t tmsr; /* 0x34 Timer Mask Set Register */
  836 + uint32_t tmcr; /* 0x38 Timer Mask Clear Register */
  837 + uint32_t tscr; /* 0x3C Timer Stop Clear Register */
  838 + uint32_t tdfr0; /* 0x40 Timer Data Full Register */
  839 + uint32_t tdhr0; /* 0x44 Timer Data Half Register */
  840 + uint32_t tcnt0; /* 0x48 Timer Counter Register */
  841 + uint32_t tcsr0; /* 0x4C Timer Control Register */
  842 + uint32_t tdfr1; /* 0x50 */
  843 + uint32_t tdhr1; /* 0x54 */
  844 + uint32_t tcnt1; /* 0x58 */
  845 + uint32_t tcsr1; /* 0x5C */
  846 + uint32_t tdfr2; /* 0x60 */
  847 + uint32_t tdhr2; /* 0x64 */
  848 + uint32_t tcnt2; /* 0x68 */
  849 + uint32_t tcsr2; /* 0x6C */
  850 + uint32_t tdfr3; /* 0x70 */
  851 + uint32_t tdhr3; /* 0x74 */
  852 + uint32_t tcnt3; /* 0x78 */
  853 + uint32_t tcsr3; /* 0x7C */
  854 + uint32_t tdfr4; /* 0x80 */
  855 + uint32_t tdhr4; /* 0x84 */
  856 + uint32_t tcnt4; /* 0x88 */
  857 + uint32_t tcsr4; /* 0x8C */
  858 + uint32_t tdfr5; /* 0x90 */
  859 + uint32_t tdhr5; /* 0x94 */
  860 + uint32_t tcnt5; /* 0x98 */
  861 + uint32_t tcsr5; /* 0x9C */
  862 +};
  863 +
  864 +/* WDT (WatchDog Timer) */
  865 +struct jz4740_wdt {
  866 + uint16_t tdr; /* 0x00 watchdog timer data reg*/
  867 + uint16_t pad00;
  868 + uint8_t tcer; /* 0x04 watchdog counter enable reg*/
  869 + uint8_t pad01[3];
  870 + uint16_t tcnt; /* 0x08 watchdog timer counter*/
  871 + uint16_t pad02;
  872 + uint16_t tcsr; /* 0x0C watchdog timer control reg*/
  873 + uint16_t pad03;
  874 +};
  875 +
  876 +struct jz4740_uart {
  877 + uint8_t rbr_thr_dllr;
  878 + /* 0x00 R 8b receive buffer reg */
  879 + /* 0x00 W 8b transmit hold reg */
  880 + /* 0x00 RW 8b divisor latch low reg */
  881 + uint8_t pad00[3];
  882 + uint8_t dlhr_ier;
  883 + /* 0x04 RW 8b divisor latch high reg */
  884 + /* 0x04 RW 8b interrupt enable reg */
  885 + uint8_t pad01[3];
  886 + uint8_t iir_fcr;
  887 + /* 0x08 R 8b interrupt identification reg */
  888 + /* 0x08 W 8b FIFO control reg */
  889 + uint8_t pad02[3];
  890 + uint8_t lcr; /* 0x0C RW 8b Line control reg */
  891 + uint8_t pad03[3];
  892 + uint8_t mcr; /* 0x10 RW 8b modem control reg */
  893 + uint8_t pad04[3];
  894 + uint8_t lsr; /* 0x14 R 8b line status reg */
  895 + uint8_t pad05[3];
  896 + uint8_t msr; /* 0x18 R 8b modem status reg */
  897 + uint8_t pad06[3];
  898 + uint8_t spr; /* 0x1C RW 8b scratch pad reg */
  899 + uint8_t pad07[3];
  900 + uint8_t isr; /* 0x20 RW 8b infrared selection reg */
  901 + uint8_t pad08[3];
  902 + uint8_t umr; /* 0x24 RW 8b */
  903 +};
  904 +
  905 +/* MSC */
  906 +struct jz4740_msc {
  907 + uint16_t strpcl;/* 0x00 */
  908 + uint32_t stat; /* 0x04 */
  909 + uint16_t clkrt; /* 0x08 */
  910 + uint32_t cmdat; /* 0x0C */
  911 + uint16_t resto; /* 0x10 */
  912 + uint16_t rdto; /* 0x14 */
  913 + uint16_t blklen;/* 0x18 */
  914 + uint16_t nob; /* 0x1C */
  915 + uint16_t snob; /* 0x20 */
  916 + uint16_t imask; /* 0x24 */
  917 + uint16_t ireg; /* 0x28 */
  918 + uint8_t cmd; /* 0x2C */
  919 + uint32_t arg; /* 0x30 */
  920 + uint16_t res; /* 0x34 */
  921 + uint32_t rxfifo;/* 0x38 */
  922 + uint32_t txfifo;/* 0x3C */
  923 +};
  924 +
  925 +/* External Memory Controller */
  926 +struct jz4740_emc {
  927 + uint32_t bcr; /* 0x00 BCR */
  928 + uint32_t pad00[3];
  929 + uint32_t smcr[5];
  930 + /* x10 Static Memory Control Register 0 */
  931 + /* x14 Static Memory Control Register 1 */
  932 + /* x18 Static Memory Control Register 2 */
  933 + /* x1c Static Memory Control Register 3 */
  934 + /* x20 Static Memory Control Register 4 */
  935 + uint32_t pad01[3];
  936 + uint32_t sacr[5];
  937 + /* x30 Static Memory Bank 0 Addr Config Reg */
  938 + /* x34 Static Memory Bank 1 Addr Config Reg */
  939 + /* x38 Static Memory Bank 2 Addr Config Reg */
  940 + /* x3c Static Memory Bank 3 Addr Config Reg */
  941 + /* x40 Static Memory Bank 4 Addr Config Reg */
  942 + uint32_t pad02[3];
  943 + uint32_t nfcsr; /* x050 NAND Flash Control/Status Register */
  944 +
  945 + uint32_t pad03[11];
  946 + uint32_t dmcr; /* x80 DRAM Control Register */
  947 + uint16_t rtcsr; /* x84 Refresh Time Control/Status Register */
  948 + uint16_t pad04;
  949 + uint16_t rtcnt; /* x88 Refresh Timer Counter */
  950 + uint16_t pad05;
  951 + uint16_t rtcor; /* x8c Refresh Time Constant Register */
  952 + uint16_t pad06;
  953 + uint32_t dmar0; /* x90 SDRAM Bank 0 Addr Config Register */
  954 + uint32_t pad07[27];
  955 + uint32_t nfecr; /* x100 NAND Flash ECC Control Register */
  956 + uint32_t nfecc; /* x104 NAND Flash ECC Data Register */
  957 + uint8_t nfpar[12];
  958 + /* x108 NAND Flash RS Parity 0 Register */
  959 + /* x10c NAND Flash RS Parity 1 Register */
  960 + /* x110 NAND Flash RS Parity 2 Register */
  961 + uint32_t nfints; /* x114 NAND Flash Interrupt Status Register */
  962 + uint32_t nfinte; /* x118 NAND Flash Interrupt Enable Register */
  963 + uint32_t nferr[4];
  964 + /* x11c NAND Flash RS Error Report 0 Register */
  965 + /* x120 NAND Flash RS Error Report 1 Register */
  966 + /* x124 NAND Flash RS Error Report 2 Register */
  967 + /* x128 NAND Flash RS Error Report 3 Register */
  968 +};
  969 +
  970 +#define __gpio_as_nand() \
  971 +do { \
  972 + writel(0x02018000, GPIO_PXFUNS(1)); \
  973 + writel(0x02018000, GPIO_PXSELC(1)); \
  974 + writel(0x02018000, GPIO_PXPES(1)); \
  975 + writel(0x30000000, GPIO_PXFUNS(2)); \
  976 + writel(0x30000000, GPIO_PXSELC(2)); \
  977 + writel(0x30000000, GPIO_PXPES(2)); \
  978 + writel(0x40000000, GPIO_PXFUNC(2)); \
  979 + writel(0x40000000, GPIO_PXSELC(2)); \
  980 + writel(0x40000000, GPIO_PXDIRC(2)); \
  981 + writel(0x40000000, GPIO_PXPES(2)); \
  982 + writel(0x00400000, GPIO_PXFUNS(1)); \
  983 + writel(0x00400000, GPIO_PXSELC(1)); \
  984 +} while (0)
  985 +
  986 +#define __gpio_as_sdram_16bit_4720() \
  987 +do { \
  988 + writel(0x5442bfaa, GPIO_PXFUNS(0)); \
  989 + writel(0x5442bfaa, GPIO_PXSELC(0)); \
  990 + writel(0x5442bfaa, GPIO_PXPES(0)); \
  991 + writel(0x81f9ffff, GPIO_PXFUNS(1)); \
  992 + writel(0x81f9ffff, GPIO_PXSELC(1)); \
  993 + writel(0x81f9ffff, GPIO_PXPES(1)); \
  994 + writel(0x01000000, GPIO_PXFUNS(2)); \
  995 + writel(0x01000000, GPIO_PXSELC(2)); \
  996 + writel(0x01000000, GPIO_PXPES(2)); \
  997 +} while (0)
  998 +
  999 +#define __gpio_as_lcd_18bit() \
  1000 +do { \
  1001 + writel(0x003fffff, GPIO_PXFUNS(2)); \
  1002 + writel(0x003fffff, GPIO_PXSELC(2)); \
  1003 + writel(0x003fffff, GPIO_PXPES(2)); \
  1004 +} while (0)
  1005 +
  1006 +/* MSC_CMD, MSC_CLK, MSC_D0 ~ MSC_D3 */
  1007 +#define __gpio_as_msc() \
  1008 +do { \
  1009 + writel(0x00003f00, GPIO_PXFUNS(3)); \
  1010 + writel(0x00003f00, GPIO_PXSELC(3)); \
  1011 + writel(0x00003f00, GPIO_PXPES(3)); \
  1012 +} while (0)
  1013 +
  1014 +#define __gpio_get_port(p) (readl(GPIO_PXPIN(p)))
  1015 +
  1016 +#define __gpio_disable_pull(n) \
  1017 +do { \
  1018 + unsigned int p, o; \
  1019 + p = (n) / 32; \
  1020 + o = (n) % 32; \
  1021 + writel((1 << o), GPIO_PXPES(p)); \
  1022 +} while (0)
  1023 +
  1024 +#define __gpio_enable_pull(n) \
  1025 +do { \
  1026 + unsigned int p, o; \
  1027 + p = (n) / 32; \
  1028 + o = (n) % 32; \
  1029 + writel(1 << (o), GPIO_PXPEC(p)); \
  1030 +} while (0)
  1031 +
  1032 +#define __gpio_port_as_output(p, o) \
  1033 +do { \
  1034 + writel(1 << (o), GPIO_PXFUNC(p)); \
  1035 + writel(1 << (o), GPIO_PXSELC(p)); \
  1036 + writel(1 << (o), GPIO_PXDIRS(p)); \
  1037 +} while (0)
  1038 +
  1039 +#define __gpio_port_as_input(p, o) \
  1040 +do { \
  1041 + writel(1 << (o), GPIO_PXFUNC(p)); \
  1042 + writel(1 << (o), GPIO_PXSELC(p)); \
  1043 + writel(1 << (o), GPIO_PXDIRC(p)); \
  1044 +} while (0)
  1045 +
  1046 +#define __gpio_as_output(n) \
  1047 +do { \
  1048 + unsigned int p, o; \
  1049 + p = (n) / 32; \
  1050 + o = (n) % 32; \
  1051 + __gpio_port_as_output(p, o); \
  1052 +} while (0)
  1053 +
  1054 +#define __gpio_as_input(n) \
  1055 +do { \
  1056 + unsigned int p, o; \
  1057 + p = (n) / 32; \
  1058 + o = (n) % 32; \
  1059 + __gpio_port_as_input(p, o); \
  1060 +} while (0)
  1061 +
  1062 +#define __gpio_set_pin(n) \
  1063 +do { \
  1064 + unsigned int p, o; \
  1065 + p = (n) / 32; \
  1066 + o = (n) % 32; \
  1067 + writel((1 << o), GPIO_PXDATS(p)); \
  1068 +} while (0)
  1069 +
  1070 +#define __gpio_clear_pin(n) \
  1071 +do { \
  1072 + unsigned int p, o; \
  1073 + p = (n) / 32; \
  1074 + o = (n) % 32; \
  1075 + writel((1 << o), GPIO_PXDATC(p)); \
  1076 +} while (0)
  1077 +
  1078 +#define __gpio_get_pin(n) \
  1079 +({ \
  1080 + unsigned int p, o, v; \
  1081 + p = (n) / 32; \
  1082 + o = (n) % 32; \
  1083 + if (__gpio_get_port(p) & (1 << o)) \
  1084 + v = 1; \
  1085 + else \
  1086 + v = 0; \
  1087 + v; \
  1088 +})
  1089 +
  1090 +#define __gpio_as_uart0() \
  1091 +do { \
  1092 + writel(0x06000000, GPIO_PXFUNS(3)); \
  1093 + writel(0x06000000, GPIO_PXSELS(3)); \
  1094 + writel(0x06000000, GPIO_PXPES(3)); \
  1095 +} while (0)
  1096 +
  1097 +#define __gpio_jtag_to_uart0() \
  1098 +do { \
  1099 + writel(0x80000000, GPIO_PXSELS(2)); \
  1100 +} while (0)
  1101 +
  1102 +/* Clock Control Register */
  1103 +#define __cpm_get_pllm() \
  1104 + ((readl(JZ4740_CPM_BASE + 0x10) & CPM_CPPCR_PLLM_MASK) \
  1105 + >> CPM_CPPCR_PLLM_BIT)
  1106 +#define __cpm_get_plln() \
  1107 + ((readl(JZ4740_CPM_BASE + 0x10) & CPM_CPPCR_PLLN_MASK) \
  1108 + >> CPM_CPPCR_PLLN_BIT)
  1109 +#define __cpm_get_pllod() \
  1110 + ((readl(JZ4740_CPM_BASE + 0x10) & CPM_CPPCR_PLLOD_MASK) \
  1111 + >> CPM_CPPCR_PLLOD_BIT)
  1112 +#define __cpm_get_hdiv() \
  1113 + ((readl(JZ4740_CPM_BASE + 0x00) & CPM_CPCCR_HDIV_MASK) \
  1114 + >> CPM_CPCCR_HDIV_BIT)
  1115 +#define __cpm_get_pdiv() \
  1116 + ((readl(JZ4740_CPM_BASE + 0x00) & CPM_CPCCR_PDIV_MASK) \
  1117 + >> CPM_CPCCR_PDIV_BIT)
  1118 +#define __cpm_get_cdiv() \
  1119 + ((readl(JZ4740_CPM_BASE + 0x00) & CPM_CPCCR_CDIV_MASK) \
  1120 + >> CPM_CPCCR_CDIV_BIT)
  1121 +#define __cpm_get_mdiv() \
  1122 + ((readl(JZ4740_CPM_BASE + 0x00) & CPM_CPCCR_MDIV_MASK) \
  1123 + >> CPM_CPCCR_MDIV_BIT)
  1124 +
  1125 +static inline unsigned int __cpm_get_pllout(void)
  1126 +{
  1127 + uint32_t m, n, no, pllout;
  1128 + uint32_t od[4] = {1, 2, 2, 4};
  1129 +
  1130 + struct jz4740_cpm *cpm = (struct jz4740_cpm *)JZ4740_CPM_BASE;
  1131 + uint32_t cppcr = readl(&cpm->cppcr);
  1132 +
  1133 + if ((cppcr & CPM_CPPCR_PLLEN) && !(cppcr & CPM_CPPCR_PLLBP)) {
  1134 + m = __cpm_get_pllm() + 2;
  1135 + n = __cpm_get_plln() + 2;
  1136 + no = od[__cpm_get_pllod()];
  1137 + pllout = (CONFIG_SYS_EXTAL / (n * no)) * m;
  1138 + } else
  1139 + pllout = CONFIG_SYS_EXTAL;
  1140 +
  1141 + return pllout;
  1142 +}
  1143 +
  1144 +extern void pll_init(void);
  1145 +extern void sdram_init(void);
  1146 +extern void calc_clocks(void);
  1147 +extern void rtc_init(void);
  1148 +
  1149 +#endif /* !__ASSEMBLY__ */
  1150 +#endif /* __JZ4740_H__ */
board/qi/qi_lb60/Makefile
Diff comments   View file @ d8fffa0
  1 +#
  2 +# (C) Copyright 2006
  3 +# Ingenic Semiconductor, <jlwei@ingenic.cn>
  4 +#
  5 +# This program is free software; you can redistribute it and/or
  6 +# modify it under the terms of the GNU General Public License as
  7 +# published by the Free Software Foundation; either version 2 of
  8 +# the License, or (at your option) any later version.
  9 +#
  10 +# This program is distributed in the hope that it will be useful,
  11 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13 +# GNU General Public License for more details.
  14 +#
  15 +# You should have received a copy of the GNU General Public License
  16 +# along with this program; if not, write to the Free Software
  17 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18 +# MA 02111-1307 USA
  19 +#
  20 +
  21 +include $(TOPDIR)/config.mk
  22 +
  23 +LIB = $(obj)lib$(BOARD).o
  24 +
  25 +COBJS := $(BOARD).o
  26 +
  27 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
  28 +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
  29 +
  30 +$(LIB): $(obj).depend $(OBJS) $(SOBJS)
  31 + $(call cmd_link_o_target, $(OBJS))
  32 +
  33 +clean:
  34 + rm -f $(SOBJS) $(OBJS)
  35 +
  36 +distclean: clean
  37 + rm -f $(LIB) core *.bak $(obj).depend
  38 +#########################################################################
  39 +
  40 +# defines $(obj).depend target
  41 +include $(SRCTREE)/rules.mk
  42 +
  43 +sinclude $(obj).depend
  44 +
  45 +#########################################################################
board/qi/qi_lb60/config.mk
Diff comments   View file @ d8fffa0
  1 +#
  2 +# (C) Copyright 2006 Qi Hardware, Inc.
  3 +# Author: Xiangfu Liu <xiangfu.z@gmail.com>
  4 +#
  5 +# This program is free software; you can redistribute it and/or
  6 +# modify it under the terms of the GNU General Public License as
  7 +# published by the Free Software Foundation; either version 2 of
  8 +# the License, or (at your option) any later version.
  9 +#
  10 +# This program is distributed in the hope that it will be useful,
  11 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13 +# GNU General Public License for more details.
  14 +#
  15 +# You should have received a copy of the GNU General Public License
  16 +# along with this program; if not, write to the Free Software
  17 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18 +# MA 02111-1307 USA
  19 +#
  20 +
  21 +#
  22 +# Qi Hardware, Inc. Ben NanoNote (QI_LB60)
  23 +#
  24 +
  25 +ifndef TEXT_BASE
  26 +# ROM version
  27 +# TEXT_BASE = 0x88000000
  28 +
  29 +# RAM version
  30 +TEXT_BASE = 0x80100000
  31 +endif
board/qi/qi_lb60/qi_lb60.c
Diff comments   View file @ d8fffa0
  1 +/*
  2 + * Authors: Xiangfu Liu <xiangfu@sharism.cc>
  3 + *
  4 + * This program is free software; you can redistribute it and/or
  5 + * modify it under the terms of the GNU General Public License
  6 + * as published by the Free Software Foundation; either version
  7 + * 3 of the License, or (at your option) any later version.
  8 + */
  9 +
  10 +#include <common.h>
  11 +#include <asm/io.h>
  12 +#include <asm/jz4740.h>
  13 +
  14 +DECLARE_GLOBAL_DATA_PTR;
  15 +
  16 +static void gpio_init(void)
  17 +{
  18 + unsigned int i;
  19 +
  20 + /* Initialize NAND Flash Pins */
  21 + __gpio_as_nand();
  22 +
  23 + /* Initialize SDRAM pins */
  24 + __gpio_as_sdram_16bit_4720();
  25 +
  26 + /* Initialize LCD pins */
  27 + __gpio_as_lcd_18bit();
  28 +
  29 + /* Initialize MSC pins */
  30 + __gpio_as_msc();
  31 +
  32 + /* Initialize Other pins */
  33 + for (i = 0; i < 7; i++) {
  34 + __gpio_as_input(GPIO_KEYIN_BASE + i);
  35 + __gpio_enable_pull(GPIO_KEYIN_BASE + i);
  36 + }
  37 +
  38 + for (i = 0; i < 8; i++) {
  39 + __gpio_as_output(GPIO_KEYOUT_BASE + i);
  40 + __gpio_clear_pin(GPIO_KEYOUT_BASE + i);
  41 + }
  42 +
  43 + __gpio_as_input(GPIO_KEYIN_8);
  44 + __gpio_enable_pull(GPIO_KEYIN_8);
  45 +
  46 + /* enable the TP4, TP5 as UART0 */
  47 + __gpio_jtag_to_uart0();
  48 +
  49 + __gpio_as_output(GPIO_AUDIO_POP);
  50 + __gpio_set_pin(GPIO_AUDIO_POP);
  51 +
  52 + __gpio_as_output(GPIO_LCD_CS);
  53 + __gpio_clear_pin(GPIO_LCD_CS);
  54 +
  55 + __gpio_as_output(GPIO_AMP_EN);
  56 + __gpio_clear_pin(GPIO_AMP_EN);
  57 +
  58 + __gpio_as_output(GPIO_SDPW_EN);
  59 + __gpio_disable_pull(GPIO_SDPW_EN);
  60 + __gpio_clear_pin(GPIO_SDPW_EN);
  61 +
  62 + __gpio_as_input(GPIO_SD_DETECT);
  63 + __gpio_disable_pull(GPIO_SD_DETECT);
  64 +
  65 + __gpio_as_input(GPIO_USB_DETECT);
  66 + __gpio_enable_pull(GPIO_USB_DETECT);
  67 +}
  68 +
  69 +static void cpm_init(void)
  70 +{
  71 + struct jz4740_cpm *cpm = (struct jz4740_cpm *)JZ4740_CPM_BASE;
  72 + uint32_t reg = readw(&cpm->clkgr);
  73 +
  74 + reg |= CPM_CLKGR_IPU |
  75 + CPM_CLKGR_CIM |
  76 + CPM_CLKGR_I2C |
  77 + CPM_CLKGR_SSI |
  78 + CPM_CLKGR_UART1 |
  79 + CPM_CLKGR_SADC |
  80 + CPM_CLKGR_UHC |
  81 + CPM_CLKGR_UDC |
  82 + CPM_CLKGR_AIC1;
  83 +
  84 + writew(reg, &cpm->clkgr);
  85 +}
  86 +
  87 +int board_early_init_f(void)
  88 +{
  89 + gpio_init();
  90 + cpm_init();
  91 + calc_clocks(); /* calc the clocks */
  92 + rtc_init(); /* init rtc on any reset */
  93 +
  94 + return 0;
  95 +}
  96 +
  97 +/* U-Boot common routines */
  98 +int checkboard(void)
  99 +{
  100 + printf("Board: Qi LB60 (Ingenic XBurst Jz4740 SoC, Speed %ld MHz)\n",
  101 + gd->cpu_clk / 1000000);
  102 +
  103 + return 0;
  104 +}
board/qi/qi_lb60/u-boot.lds
Diff comments   View file @ d8fffa0
  1 +/*
  2 + * (C) Copyright 2006
  3 + * Ingenic Semiconductor, <jlwei@ingenic.cn>
  4 + *
  5 + * This program is free software; you can redistribute it and/or
  6 + * modify it under the terms of the GNU General Public License as
  7 + * published by the Free Software Foundation; either version 2 of
  8 + * the License, or (at your option) any later version.
  9 + *
  10 + * This program is distributed in the hope that it will be useful,
  11 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13 + * GNU General Public License for more details.
  14 + *
  15 + * You should have received a copy of the GNU General Public License
  16 + * along with this program; if not, write to the Free Software
  17 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18 + * MA 02111-1307 USA
  19 + */
  20 +
  21 +OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
  22 +
  23 +OUTPUT_ARCH(mips)
  24 +ENTRY(_start)
  25 +SECTIONS
  26 +{
  27 + . = 0x00000000;
  28 +
  29 + . = ALIGN(4);
  30 + .text :
  31 + {
  32 + *(.text*)
  33 + }
  34 +
  35 + . = ALIGN(4);
  36 + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
  37 +
  38 + . = ALIGN(4);
  39 + .data : { *(.data*) }
  40 +
  41 + . = .;
  42 + _gp = ALIGN(16) + 0x7ff0;
  43 +
  44 + __got_start = .;
  45 + .got : { *(.got) }
  46 + __got_end = .;
  47 +
  48 + .sdata : { *(.sdata*) }
  49 +
  50 + __u_boot_cmd_start = .;
  51 + .u_boot_cmd : { *(.u_boot_cmd) }
  52 + __u_boot_cmd_end = .;
  53 +
  54 + uboot_end_data = .;
  55 + num_got_entries = (__got_end - __got_start) >> 2;
  56 +
  57 + . = ALIGN(4);
  58 + .sbss : { *(.sbss*) }
  59 + .bss : { *(.bss*) . = ALIGN(4); }
  60 + uboot_end = .;
  61 +}
... ... @@ -302,6 +302,7 @@
302 302 vct_platinumavc_small mips mips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_SMALL_IMAGE
303 303 vct_platinumavc_onenand mips mips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND
304 304 vct_platinumavc_onenand_small mips mips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND,VCT_SMALL_IMAGE
  305 +qi_lb60 mips xburst qi_lb60 qi
305 306 nios2-generic nios2 nios2 nios2-generic altera
306 307 PCI5441 nios2 nios2 pci5441 psyent
307 308 PK1C20 nios2 nios2 pk1c20 psyent
drivers/mtd/nand/Makefile
Diff comments   View file @ d8fffa0
... ... @@ -45,6 +45,7 @@
45 45 COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
46 46 COBJS-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o
47 47 COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
  48 +COBJS-$(CONFIG_NAND_JZ4740) += jz4740_nand.o
48 49 COBJS-$(CONFIG_NAND_KB9202) += kb9202_nand.o
49 50 COBJS-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
50 51 COBJS-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o
drivers/mtd/nand/jz4740_nand.c
Diff comments   View file @ d8fffa0
  1 +/*
  2 + * Platform independend driver for JZ4740.
  3 + *
  4 + * Copyright (c) 2007 Ingenic Semiconductor Inc.
  5 + * Author: <jlwei@ingenic.cn>
  6 + *
  7 + * This program is free software; you can redistribute it and/or
  8 + * modify it under the terms of the GNU General Public License as
  9 + * published by the Free Software Foundation; either version 2 of
  10 + * the License, or (at your option) any later version.
  11 + */
  12 +#include <common.h>
  13 +
  14 +#include <nand.h>
  15 +#include <asm/io.h>
  16 +#include <asm/jz4740.h>
  17 +
  18 +#define JZ_NAND_DATA_ADDR ((void __iomem *)0xB8000000)
  19 +#define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000)
  20 +#define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x10000)
  21 +
  22 +#define BIT(x) (1 << (x))
  23 +#define JZ_NAND_ECC_CTRL_ENCODING BIT(3)
  24 +#define JZ_NAND_ECC_CTRL_RS BIT(2)
  25 +#define JZ_NAND_ECC_CTRL_RESET BIT(1)
  26 +#define JZ_NAND_ECC_CTRL_ENABLE BIT(0)
  27 +
  28 +#define EMC_SMCR1_OPT_NAND 0x094c4400
  29 +/* Optimize the timing of nand */
  30 +
  31 +static struct jz4740_emc * emc = (struct jz4740_emc *)JZ4740_EMC_BASE;
  32 +
  33 +static struct nand_ecclayout qi_lb60_ecclayout_2gb = {
  34 + .eccbytes = 72,
  35 + .eccpos = {
  36 + 12, 13, 14, 15, 16, 17, 18, 19,
  37 + 20, 21, 22, 23, 24, 25, 26, 27,
  38 + 28, 29, 30, 31, 32, 33, 34, 35,
  39 + 36, 37, 38, 39, 40, 41, 42, 43,
  40 + 44, 45, 46, 47, 48, 49, 50, 51,
  41 + 52, 53, 54, 55, 56, 57, 58, 59,
  42 + 60, 61, 62, 63, 64, 65, 66, 67,
  43 + 68, 69, 70, 71, 72, 73, 74, 75,
  44 + 76, 77, 78, 79, 80, 81, 82, 83 },
  45 + .oobfree = {
  46 + {.offset = 2,
  47 + .length = 10 },
  48 + {.offset = 84,
  49 + .length = 44 } }
  50 +};
  51 +
  52 +static int is_reading;
  53 +
  54 +static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
  55 +{
  56 + struct nand_chip *this = mtd->priv;
  57 + uint32_t reg;
  58 +
  59 + if (ctrl & NAND_CTRL_CHANGE) {
  60 + if (ctrl & NAND_ALE)
  61 + this->IO_ADDR_W = JZ_NAND_ADDR_ADDR;
  62 + else if (ctrl & NAND_CLE)
  63 + this->IO_ADDR_W = JZ_NAND_CMD_ADDR;
  64 + else
  65 + this->IO_ADDR_W = JZ_NAND_DATA_ADDR;
  66 +
  67 + reg = readl(&emc->nfcsr);
  68 + if (ctrl & NAND_NCE)
  69 + reg |= EMC_NFCSR_NFCE1;
  70 + else
  71 + reg &= ~EMC_NFCSR_NFCE1;
  72 + writel(reg, &emc->nfcsr);
  73 + }
  74 +
  75 + if (cmd != NAND_CMD_NONE)
  76 + writeb(cmd, this->IO_ADDR_W);
  77 +}
  78 +
  79 +static int jz_nand_device_ready(struct mtd_info *mtd)
  80 +{
  81 + return (readl(GPIO_PXPIN(2)) & 0x40000000) ? 1 : 0;
  82 +}
  83 +
  84 +void board_nand_select_device(struct nand_chip *nand, int chip)
  85 +{
  86 + /*
  87 + * Don't use "chip" to address the NAND device,
  88 + * generate the cs from the address where it is encoded.
  89 + */
  90 +}
  91 +
  92 +static int jz_nand_rs_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
  93 + u_char *ecc_code)
  94 +{
  95 + uint32_t status;
  96 + int i;
  97 +
  98 + if (is_reading)
  99 + return 0;
  100 +
  101 + do {
  102 + status = readl(&emc->nfints);
  103 + } while (!(status & EMC_NFINTS_ENCF));
  104 +
  105 + /* disable ecc */
  106 + writel(readl(&emc->nfecr) & ~EMC_NFECR_ECCE, &emc->nfecr);
  107 +
  108 + for (i = 0; i < 9; i++)
  109 + ecc_code[i] = readb(&emc->nfpar[i]);
  110 +
  111 + return 0;
  112 +}
  113 +
  114 +static void jz_nand_hwctl(struct mtd_info *mtd, int mode)
  115 +{
  116 + uint32_t reg;
  117 +
  118 + writel(0, &emc->nfints);
  119 + reg = readl(&emc->nfecr);
  120 + reg |= JZ_NAND_ECC_CTRL_RESET;
  121 + reg |= JZ_NAND_ECC_CTRL_ENABLE;
  122 + reg |= JZ_NAND_ECC_CTRL_RS;
  123 +
  124 + switch (mode) {
  125 + case NAND_ECC_READ:
  126 + reg &= ~JZ_NAND_ECC_CTRL_ENCODING;
  127 + is_reading = 1;
  128 + break;
  129 + case NAND_ECC_WRITE:
  130 + reg |= JZ_NAND_ECC_CTRL_ENCODING;
  131 + is_reading = 0;
  132 + break;
  133 + default:
  134 + break;
  135 + }
  136 +
  137 + writel(reg, &emc->nfecr);
  138 +}
  139 +
  140 +/* Correct 1~9-bit errors in 512-bytes data */
  141 +static void jz_rs_correct(unsigned char *dat, int idx, int mask)
  142 +{
  143 + int i;
  144 +
  145 + idx--;
  146 +
  147 + i = idx + (idx >> 3);
  148 + if (i >= 512)
  149 + return;
  150 +
  151 + mask <<= (idx & 0x7);
  152 +
  153 + dat[i] ^= mask & 0xff;
  154 + if (i < 511)
  155 + dat[i + 1] ^= (mask >> 8) & 0xff;
  156 +}
  157 +
  158 +static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
  159 + u_char *read_ecc, u_char *calc_ecc)
  160 +{
  161 + int k;
  162 + uint32_t errcnt, index, mask, status;
  163 +
  164 + /* Set PAR values */
  165 + const uint8_t all_ff_ecc[] = {
  166 + 0xcd, 0x9d, 0x90, 0x58, 0xf4, 0x8b, 0xff, 0xb7, 0x6f };
  167 +
  168 + if (read_ecc[0] == 0xff && read_ecc[1] == 0xff &&
  169 + read_ecc[2] == 0xff && read_ecc[3] == 0xff &&
  170 + read_ecc[4] == 0xff && read_ecc[5] == 0xff &&
  171 + read_ecc[6] == 0xff && read_ecc[7] == 0xff &&
  172 + read_ecc[8] == 0xff) {
  173 + for (k = 0; k < 9; k++)
  174 + writeb(all_ff_ecc[k], &emc->nfpar[k]);
  175 + } else {
  176 + for (k = 0; k < 9; k++)
  177 + writeb(read_ecc[k], &emc->nfpar[k]);
  178 + }
  179 + /* Set PRDY */
  180 + writel(readl(&emc->nfecr) | EMC_NFECR_PRDY, &emc->nfecr);
  181 +
  182 + /* Wait for completion */
  183 + do {
  184 + status = readl(&emc->nfints);
  185 + } while (!(status & EMC_NFINTS_DECF));
  186 +
  187 + /* disable ecc */
  188 + writel(readl(&emc->nfecr) & ~EMC_NFECR_ECCE, &emc->nfecr);
  189 +
  190 + /* Check decoding */
  191 + if (!(status & EMC_NFINTS_ERR))
  192 + return 0;
  193 +
  194 + if (status & EMC_NFINTS_UNCOR) {
  195 + printf("uncorrectable ecc\n");
  196 + return -1;
  197 + }
  198 +
  199 + errcnt = (status & EMC_NFINTS_ERRCNT_MASK) >> EMC_NFINTS_ERRCNT_BIT;
  200 +
  201 + switch (errcnt) {
  202 + case 4:
  203 + index = (readl(&emc->nferr[3]) & EMC_NFERR_INDEX_MASK) >>
  204 + EMC_NFERR_INDEX_BIT;
  205 + mask = (readl(&emc->nferr[3]) & EMC_NFERR_MASK_MASK) >>
  206 + EMC_NFERR_MASK_BIT;
  207 + jz_rs_correct(dat, index, mask);
  208 + case 3:
  209 + index = (readl(&emc->nferr[2]) & EMC_NFERR_INDEX_MASK) >>
  210 + EMC_NFERR_INDEX_BIT;
  211 + mask = (readl(&emc->nferr[2]) & EMC_NFERR_MASK_MASK) >>
  212 + EMC_NFERR_MASK_BIT;
  213 + jz_rs_correct(dat, index, mask);
  214 + case 2:
  215 + index = (readl(&emc->nferr[1]) & EMC_NFERR_INDEX_MASK) >>
  216 + EMC_NFERR_INDEX_BIT;
  217 + mask = (readl(&emc->nferr[1]) & EMC_NFERR_MASK_MASK) >>
  218 + EMC_NFERR_MASK_BIT;
  219 + jz_rs_correct(dat, index, mask);
  220 + case 1:
  221 + index = (readl(&emc->nferr[0]) & EMC_NFERR_INDEX_MASK) >>
  222 + EMC_NFERR_INDEX_BIT;
  223 + mask = (readl(&emc->nferr[0]) & EMC_NFERR_MASK_MASK) >>
  224 + EMC_NFERR_MASK_BIT;
  225 + jz_rs_correct(dat, index, mask);
  226 + default:
  227 + break;
  228 + }
  229 +
  230 + return errcnt;
  231 +}
  232 +
  233 +/*
  234 + * Main initialization routine
  235 + */
  236 +int board_nand_init(struct nand_chip *nand)
  237 +{
  238 + uint32_t reg;
  239 +
  240 + reg = readl(&emc->nfcsr);
  241 + reg |= EMC_NFCSR_NFE1; /* EMC setup, Set NFE bit */
  242 + writel(reg, &emc->nfcsr);
  243 +
  244 + writel(EMC_SMCR1_OPT_NAND, &emc->smcr[1]);
  245 +
  246 + nand->IO_ADDR_R = JZ_NAND_DATA_ADDR;
  247 + nand->IO_ADDR_W = JZ_NAND_DATA_ADDR;
  248 + nand->cmd_ctrl = jz_nand_cmd_ctrl;
  249 + nand->dev_ready = jz_nand_device_ready;
  250 + nand->ecc.hwctl = jz_nand_hwctl;
  251 + nand->ecc.correct = jz_nand_rs_correct_data;
  252 + nand->ecc.calculate = jz_nand_rs_calculate_ecc;
  253 + nand->ecc.mode = NAND_ECC_HW_OOB_FIRST;
  254 + nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
  255 + nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
  256 + nand->ecc.layout = &qi_lb60_ecclayout_2gb;
  257 + nand->chip_delay = 50;
  258 + nand->options = NAND_USE_FLASH_BBT;
  259 +
  260 + return 0;
  261 +}
include/configs/qi_lb60.h
Diff comments   View file @ d8fffa0
  1 +/*
  2 + * Authors: Xiangfu Liu <xiangfu.z@gmail.com>
  3 + *
  4 + * This program is free software; you can redistribute it and/or
  5 + * modify it under the terms of the GNU General Public License
  6 + * as published by the Free Software Foundation; either version
  7 + * 3 of the License, or (at your option) any later version.
  8 + */
  9 +
  10 +#ifndef __CONFIG_QI_LB60_H
  11 +#define __CONFIG_QI_LB60_H
  12 +
  13 +#define CONFIG_MIPS32 /* MIPS32 CPU core */
  14 +#define CONFIG_JZSOC /* Jz SoC */
  15 +#define CONFIG_JZ4740 /* Jz4740 SoC */
  16 +#define CONFIG_NAND_JZ4740
  17 +
  18 +#define CONFIG_SYS_CPU_SPEED 336000000 /* CPU clock: 336 MHz */
  19 +#define CONFIG_SYS_EXTAL 12000000 /* EXTAL freq: 12 MHz */
  20 +#define CONFIG_SYS_HZ (CONFIG_SYS_EXTAL / 256) /* incrementer freq */
  21 +#define CONFIG_SYS_MIPS_TIMER_FREQ CONFIG_SYS_CPU_SPEED
  22 +
  23 +#define CONFIG_SYS_UART_BASE JZ4740_UART0_BASE /* Base of the UART channel */
  24 +#define CONFIG_BAUDRATE 57600
  25 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  26 +
  27 +#define CONFIG_SKIP_LOWLEVEL_INIT
  28 +#define CONFIG_BOARD_EARLY_INIT_F
  29 +#define CONFIG_SYS_NO_FLASH
  30 +#define CONFIG_SYS_FLASH_BASE 0 /* init flash_base as 0 */
  31 +#define CONFIG_ENV_OVERWRITE
  32 +
  33 +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAUL)
  34 +#define CONFIG_BOOTDELAY 0
  35 +#define CONFIG_BOOTARGS "mem=32M console=tty0 console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
  36 +#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm"
  37 +
  38 +/*
  39 + * Command line configuration.
  40 + */
  41 +#define CONFIG_CMD_BOOTD /* bootd */
  42 +#define CONFIG_CMD_CONSOLE /* coninfo */
  43 +#define CONFIG_CMD_ECHO /* echo arguments */
  44 +
  45 +#define CONFIG_CMD_LOADB /* loadb */
  46 +#define CONFIG_CMD_LOADS /* loads */
  47 +#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
  48 +#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/
  49 +#define CONFIG_CMD_RUN /* run command in env variable */
  50 +#define CONFIG_CMD_SAVEENV /* saveenv */
  51 +#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
  52 +#define CONFIG_CMD_SOURCE /* "source" command support */
  53 +#define CONFIG_CMD_NAND
  54 +
  55 +/*
  56 + * Serial download configuration
  57 + */
  58 +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  59 +
  60 +/*
  61 + * Miscellaneous configurable options
  62 + */
  63 +#define CONFIG_SYS_MAXARGS 16
  64 +#define CONFIG_SYS_LONGHELP
  65 +#define CONFIG_SYS_PROMPT "NanoNote# "
  66 +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  67 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  68 +
  69 +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
  70 +#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
  71 +
  72 +#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
  73 +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
  74 +#define CONFIG_SYS_LOAD_ADDR 0x80600000
  75 +#define CONFIG_SYS_MEMTEST_START 0x80100000
  76 +#define CONFIG_SYS_MEMTEST_END 0x80800000
  77 +
  78 +/*
  79 + * Environment
  80 + */
  81 +#define CONFIG_ENV_IS_IN_NAND /* use NAND for environment vars */
  82 +
  83 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE
  84 +/*
  85 + * if board nand flash is 1GB, set to 1
  86 + * if board nand flash is 2GB, set to 2
  87 + * for change the PAGE_SIZE and BLOCK_SIZE
  88 + * will delete when there is no 1GB flash
  89 + */
  90 +#define NANONOTE_NAND_SIZE 2
  91 +
  92 +#define CONFIG_SYS_NAND_PAGE_SIZE (2048 * NANONOTE_NAND_SIZE)
  93 +#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * NANONOTE_NAND_SIZE << 10)
  94 +/* nand bad block was marked at this page in a block, start from 0 */
  95 +#define CONFIG_SYS_NAND_BADBLOCK_PAGE 127
  96 +#define CONFIG_SYS_NAND_PAGE_COUNT 128
  97 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
  98 +/* ECC offset position in oob area, default value is 6 if it isn't defined */
  99 +#define CONFIG_SYS_NAND_ECC_POS (6 * NANONOTE_NAND_SIZE)
  100 +#define CONFIG_SYS_NAND_ECCSIZE 512
  101 +#define CONFIG_SYS_NAND_ECCBYTES 9
  102 +#define CONFIG_SYS_NAND_ECCSTEPS \
  103 + (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
  104 +#define CONFIG_SYS_NAND_ECCTOTAL \
  105 + (CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
  106 +#define CONFIG_SYS_NAND_ECCPOS \
  107 + {12, 13, 14, 15, 16, 17, 18, 19,\
  108 + 20, 21, 22, 23, 24, 25, 26, 27, \
  109 + 28, 29, 30, 31, 32, 33, 34, 35, \
  110 + 36, 37, 38, 39, 40, 41, 42, 43, \
  111 + 44, 45, 46, 47, 48, 49, 50, 51, \
  112 + 52, 53, 54, 55, 56, 57, 58, 59, \
  113 + 60, 61, 62, 63, 64, 65, 66, 67, \
  114 + 68, 69, 70, 71, 72, 73, 74, 75, \
  115 + 76, 77, 78, 79, 80, 81, 82, 83}
  116 +
  117 +#define CONFIG_SYS_NAND_OOBSIZE 128
  118 +#define CONFIG_SYS_NAND_BASE 0xB8000000
  119 +#define CONFIG_SYS_ONENAND_BASE CONFIG_SYS_NAND_BASE
  120 +#define NAND_MAX_CHIPS 1
  121 +#define CONFIG_SYS_MAX_NAND_DEVICE 1
  122 +#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl.*/
  123 +#define CONFIG_NAND_SPL_TEXT_BASE 0x80000000
  124 +
  125 +/*
  126 + * IPL (Initial Program Loader, integrated inside CPU)
  127 + * Will load first 8k from NAND (SPL) into cache and execute it from there.
  128 + *
  129 + * SPL (Secondary Program Loader)
  130 + * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
  131 + * has to fit into 8kByte. It sets up the CPU and configures the SDRAM
  132 + * controller and the NAND controller so that the special U-Boot image can be
  133 + * loaded from NAND to SDRAM.
  134 + *
  135 + * NUB (NAND U-Boot)
  136 + * This NAND U-Boot (NUB) is a special U-Boot version which can be started
  137 + * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
  138 + *
  139 + */
  140 +#define CONFIG_SYS_NAND_U_BOOT_DST 0x80100000 /* Load NUB to this addr */
  141 +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
  142 +/* Start NUB from this addr*/
  143 +
  144 +/*
  145 + * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
  146 + */
  147 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) /* Offset to RAM U-Boot image */
  148 +#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */
  149 +
  150 +#define CONFIG_ENV_SIZE (4 << 10)
  151 +#define CONFIG_ENV_OFFSET \
  152 + (CONFIG_SYS_NAND_BLOCK_SIZE + CONFIG_SYS_NAND_U_BOOT_SIZE)
  153 +#define CONFIG_ENV_OFFSET_REDUND \
  154 + (CONFIG_ENV_OFFSET + CONFIG_SYS_NAND_BLOCK_SIZE)
  155 +
  156 +#define CONFIG_SYS_TEXT_BASE 0x80100000
  157 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  158 +
  159 +/*
  160 + * SDRAM Info.
  161 + */
  162 +#define CONFIG_NR_DRAM_BANKS 1
  163 +
  164 +/*
  165 + * Cache Configuration
  166 + */
  167 +#define CONFIG_SYS_DCACHE_SIZE 16384
  168 +#define CONFIG_SYS_ICACHE_SIZE 16384
  169 +#define CONFIG_SYS_CACHELINE_SIZE 32
  170 +
  171 +/*
  172 + * GPIO definition
  173 + */
  174 +#define GPIO_LCD_CS (2 * 32 + 21)
  175 +#define GPIO_AMP_EN (3 * 32 + 4)
  176 +
  177 +#define GPIO_SDPW_EN (3 * 32 + 2)
  178 +#define GPIO_SD_DETECT (3 * 32 + 0)
  179 +
  180 +#define GPIO_BUZZ_PWM (3 * 32 + 27)
  181 +#define GPIO_USB_DETECT (3 * 32 + 28)
  182 +
  183 +#define GPIO_AUDIO_POP (1 * 32 + 29)
  184 +#define GPIO_COB_TEST (1 * 32 + 30)
  185 +
  186 +#define GPIO_KEYOUT_BASE (2 * 32 + 10)
  187 +#define GPIO_KEYIN_BASE (3 * 32 + 18)
  188 +#define GPIO_KEYIN_8 (3 * 32 + 26)
  189 +
  190 +#define GPIO_SD_CD_N GPIO_SD_DETECT /* SD Card insert detect */
  191 +#define GPIO_SD_VCC_EN_N GPIO_SDPW_EN /* SD Card Power Enable */
  192 +
  193 +#define SPEN GPIO_LCD_CS /* LCDCS :Serial command enable */
  194 +#define SPDA (2 * 32 + 22) /* LCDSCL:Serial command clock input */
  195 +#define SPCK (2 * 32 + 23) /* LCDSDA:Serial command data input */
  196 +
  197 +/* SDRAM paramters */
  198 +#define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */
  199 +#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */
  200 +#define SDRAM_ROW 13 /* Row address: 11 to 13 */
  201 +#define SDRAM_COL 9 /* Column address: 8 to 12 */
  202 +#define SDRAM_CASL 2 /* CAS latency: 2 or 3 */
  203 +
  204 +/* SDRAM Timings, unit: ns */
  205 +#define SDRAM_TRAS 45 /* RAS# Active Time */
  206 +#define SDRAM_RCD 20 /* RAS# to CAS# Delay */
  207 +#define SDRAM_TPC 20 /* RAS# Precharge Time */
  208 +#define SDRAM_TRWL 7 /* Write Latency Time */
  209 +#define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */
  210 +
  211 +#endif