09 Oct, 2014
1 commit
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By introducing CONFIG_SPI_FLASH_BAR and add related command in LUT to
enable fsl_qspi.c can handle flash size bigger that 16M. Because uboot
does not support 32bits address access, this means bank address should
be used to access bigger flash.It is hard to let qspi driver dynamically set LUT, so BRRD BRWR RDEAR
and WREAR are all supported.Signed-off-by: Peng Fan
08 Oct, 2014
1 commit
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OPCODE_BE_4K is supported. To qspi flashes which support 4k sector
erase, spi framework will use OPCODE_BE_4K command. Thus add this
support to let uboot can erase such qspi flashes.Signed-off-by: Peng Fan
25 Sep, 2014
1 commit
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Currently, flash quad bit is set in "spi_flash_validate_params" and later
at the end in the same api, we write 0 to status register for few flashes,
thereby overriding the quad bit set. This fix moves the quad bit setting
outside this api in "spi_flash_probe_slave"Signed-off-by: Sourav Poddar
Reviewed-by: Jagannadha Sutradharudu Teki
10 Sep, 2014
1 commit
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THe anatop registers structure is duplicated with CCM structure at
PLL fields.
Since we are suggested not to use the name "anatop" any longer, merge
the anatop registers to the CCM structure "mxc_ccm_reg" and use CCM
to replace anatop.Signed-off-by: Ye.Li
05 Sep, 2014
1 commit
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To fsl_qspi_write_data and fsl_qspi_ip_read, pointer txbuf and
rxbuf are not guaranteed that they are 4 Bytes aligned. Also,
it it not a good idea to cast type 'u8 *' to 'u32 *', except
we are sure that pointer type 'u8 *' is 4 Bytes aligned and
cast it to 'u32 *' will not pass memory boundary.The problem is found when using fsl_qspi_write_data to write
registers in flash devices. The err msg:data abort
pc : [] lr : []
sp : bf5512c8 ip : 0000001c fp : bf856608
r10: 87868904 r9 : bf551efc r8 : 200f048c
r7 : 00000002 r6 : bf551336 r5 : bf552a70 r4 : 00000001
r3 : 00000000 r2 : 00000060 r1 : 8783b520 r0 : 8783b520
Flags: nZCv IRQs on FIQs off Mode SVC_32
Resetting CPU ...The asm code which cause data abort is:
87822f30: e5964000 ldr r4, [r6]
From the dump msg, r6 is not 4 Bytes aligned, and data abort exception.So, Use mempcy but not unsafe type casting.
In this patch, max_write_size is assigned using txfifo to avoid possible
errors in future.Signed-off-by: Peng Fan
04 Aug, 2014
1 commit
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Let's use the i.MX common miscellaneous reset API
to reset the LCDIF block so that we may eliminate
a random hang issue at the arch_preboot_os() stage
when we disable the LCDIF. This patch also waits
for a VSYNC interrupt to guarantee the reset is
done at the VSYNC edge, which somehow makes the
LCDIF consume the display FIFO(?) and helps the
LCDIF work normally at the kernel stage.Tested-by: Jason Liu
Tested-by: Sandor Yu
Tested-by: Ye.Li
Tested-by: Guo Sally
Signed-off-by: Liu Ying
31 Jul, 2014
1 commit
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Enable pcie support in uboot on imx6sx sd boards
- enable_pcie_clock should be call before ssp_en is set,
since that ssp_en control the phy_ref clk gate, turn on
it after the source of the pcie clks are stable.
- add debug info
- add rx_eq of gpr12 on imx6sx
- there are random link down issue on imx6sx. It's
pcie ep reset issue.
solution:reset ep, then retry link can fix it.Signed-off-by: Richard Zhu
17 Jul, 2014
1 commit
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The mxc gis driver should not disable mxsfb, instead,
mxsfb could be disabled in machine layer.Signed-off-by: Liu Ying
11 Jul, 2014
1 commit
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Vadc need long time to auto standards detection,
the default standard is NTSC, if vadc connect to PAL
camera and no enough time to detect the video mode,
driver will get wrong standard.Confirmation from chip design architecture that auto detect function
is not required by rear-view camera application.Setting register vdec_stddbg standard_filte bits to 0
makes the standard detection faster, the issue duplicate
decrease to 1%.Signed-off-by: Sandor Yu
(cherry picked from commit 06735bf6724f2dad2dcbbfc188c6a17145c7126b)
17 Jun, 2014
12 commits
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Add gis module, current gis is support vadc input.
Add power down function to lcdif driver.Signed-off-by: Sandor Yu
Signed-off-by: Ye.Li -
Add pxp module.
Support csc between YUV444 and RGB888 and scaling.Signed-off-by: Sandor Yu
Signed-off-by: Ye.Li -
Add csi module.
Signed-off-by: Sandor Yu
Signed-off-by: Ye.Li -
Add vadc module.
Both PAL and NTSC mode can work.Signed-off-by: Sandor Yu
Signed-off-by: Ye.Li -
Add a new interface "mxs_lcd_panel_setup" to setup fb parameters and
specifies the LCDIF controller for multiple controllers of iMX6SX.
Pass fb parameters via "videomode" env remains work if the new interface
is not called before video initialization.Modify LCDIF clock interface "mxs_set_lcdclk" to support multiple
LCDIF controllers on iMX6SX.Signed-off-by: Ye.Li
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Add BSP codes to mx6sxsabresd to support android uboot features:
fastboot, booti and recoverySigned-off-by: Ye.Li
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For GPIO group which shared by multiple masters, it may set in RDC
to shared and semaphore required. Before access the GPIO register,
the GPIO driver must get the RDC semaphore, and release the semaphore
after the GPIO register access.When CONFIG_MXC_RDC is set, the features related to RDC semaphores
is enabled in mxc_gpio driver.Signed-off-by: Ye.Li
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1. iMX6SX enet rx have 64 bytes alignment limitation for DMA transfer.
For i.MX6SX platform, need to add below define in config file:
#define CONFIG_FEC_DMA_MINALIGN 642. Change to check READY bit in BD, not check the TDAR. On iMX6SX, FEC will
clear the TDAR prior than the READY bit of last BD. Since fec driver only
prepare two BD for transmit, this cause the BD send failed at the third
packet.Signed-off-by: Fugang Duan
Signed-off-by: Ye.Li -
Enable the Quadspi read/write/erase functions.
Add two configurations "CONFIG_QSPI_BASE" and "CONFIG_QSPI_MEMMAP_BASE"
for QSPI registers base and AHB memory base.Use "bus" and "cs" parameters to denote 4 flash chip connected on one QuadSPI:
SFA1: bus 0, cs 0
SFA2: bus 0, cs 1
SFB1: bus 1, cs 0
SFB2: bus 1, cs 1Currently in uboot, the SPI flash framework does not have way to notify the
flash size to the driver. It brings a problem for QSPI driver to set the memory
map space of each chip. In this patch, we fix the mem map space of each chip
to 64MB(total is 256MB). So for each flash device, driver support 64MB at most.In addition, because u-boot SPI flash framework only supports 24bits address mode,
and uses EAR register to switch bank for flash larger than 16MB. The QuadSPI does
not support this way when reading data from AHB address. Thus, only lower 16MB
is supported.Signed-off-by: Huang Shijie
Signed-off-by: Allen Xu
Signed-off-by: Ye.Li -
The reset value of "uSDHCx_INT_STATUS_EN" register is changed to 0
on iMX6SX. So the fsl_esdhc driver must update to set the register,
otherwise no state can be detected.Signed-off-by: Ye.Li
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To be compatible with more USB otg lines which has micro port B to
connect imx6 OTG port when imx6 working at host mode, remove the
checking for the OTG ID with the init type. Only use the init type
for the power and controller initialization.Use same EHCI register base address for various imx6 platform.
Signed-off-by: Ye.Li
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Current code use the hardcoded ECC strength which is not aligned with
the kernel.This patch use the same ECC strength as used in the kernel.
We do not support the NAND whose OOB size is larger then 512bytes.
Signed-off-by: Huang Shijie
Signed-off-by: Ye.Li
13 Jun, 2014
7 commits
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Instead of waiting for DC triple buffer to be cleared, this patch changes
to wait for a relevant DP sync flow end irq when disabling sync BG flows.
In this way, we align the implement to the FSL internal IPUv3 driver.
After applying this patch, the uboot hang up issue at the arch_preboot_os
stage on the MX6DL platforms is not observed any more.Signed-off-by: Liu Ying
Signed-off-by: Nitin Garg -
-Change HDMI video mode to VGA.
-Add pixel clock fraction part setting in IPU driver,
fix video mode timing issue.
-Add overflow state clear workaround,
fix kernel hang in HDMI driver issue.
-Correct IPU clock to 264MHz.Signed-off-by: Sandor Yu
Signed-off-by: Nitin Garg -
When configure the USDHC driver to PIO mode by defining
"CONFIG_SYS_FSL_ESDHC_USE_PIO", the SD/MMC read and write will fail.Two bugs in the driver to cause the issue:
1. The read buffer was invalidated after reading from DATAPORT register,
which should be only applied to DMA mode. The valid data in cache was
overwritten by physical memory.
2. The watermarks are not set in PIO mode, will cause according state not
be set.Signed-off-by: Ye.Li
(cherry picked from commit e2ced39867a3001390bd23069e56b513ed268bb0)Signed-off-by: Nitin Garg
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When booting in eMMC fast boot, the uboot v2013.04 always hangs.
The root cause is that MMC host does not exit from boot mode after
bootrom loading image. So the first command 'CMD0' sent
in uboot will pull down the CMD line to low and cause errors.This patch cleans the MMC boot register in "mmc_init" to put the
MMC host back to normal mode.Signed-off-by: Ye Li
Signed-off-by: Nitin Garg -
Implement simple functionalities for MAX7310 GPIO input and output.
Because MAX7310 is a off-chip device and need to co-exist with
on-chip GPIO, new APIs are added specifically for expander device.CONFIG_MAX7310_IOEXP is used to enable the MAX7310 driver. The I2C
related configurations also need to set together.Signed-off-by: Ye.Li
Signed-off-by: Nitin Garg -
Set Power polarity in CTRL register to active-high to control
the off-chip power switch.Update USB base address to support imx6sl.
Signed-off-by: Nitin Garg
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Support android features:
fastboot, booti command and recovery for sabresd SD, sabresd eMMC,
sabreauto SD, sabreauto NAND.For all booting media (SD, eMMC, NAND), inherits the partitions layout
from v2009.08. Fastboot will detect the booting media to replace
hardcoding fastboot device. SATA is not supported.FDT is supported to use the "unused" fields in bootimg header which
requires the FDT to be combined into the boot.img.
For non-FDT boot.img, the "unused" fields should left to NULL and is
compatible to boot.Signed-off-by: Ye.Li
Signed-off-by: Nitin Garg
28 May, 2014
3 commits
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i.MX6sl evk has keyboards on the board, so add mxc_keyb driver to
support key press checking.Signed-off-by: Nitin Garg
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Add EPDC splash screen feature for MX6SL EVK, and MX6DL SABRESD board.
- Currently, splash screen consists of a simple black border
around a white screen. Done this way to save in memory footprint.- EPDC splash screen is disabled by default in the config file for MX6DL_SABRESD
and MX6SL_EVK. If left enabled, the U-Boot image will not boot correctly
(hang), since some additional content on the boot device (waveform file) is
required for EPDC splash to work correctly.Please refer to Linux Reference Manual for how to flash WAVEFORM file.
Signed-off-by: Robby Cai
Signed-off-by: Nitin Garg -
Android fastboot leans on the USB gadget driver to communicate with host. Porting
the imx_udc driver from v2009.08 with two changes: adding resource/memory release
APIs and replacing the uncached memory with cache flush&invalidate operations.Pins and Clocks initialization are added to support boards:
mx6qdlsabresd, mx6qdlsabreauto, mx6slevkSigned-off-by: Ye.Li
Signed-off-by: Nitin Garg
14 Apr, 2014
1 commit
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This is regression of commit 2035d77d i2c: sh_i2c: Update to new CONFIG_SYS_I2C framework
Before commit 2035d77d, i2c probe command works properly on kzm9g board.
KZM-A9-GT# i2c probe
Valid chip addresses: 0C 12 1D 32 39 3D 40 60After commit 2035d77d, i2c probe command does not work.
KZM-A9-GT# i2c probe
Valid chip addresses: 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7Fsh_i2c_probe() calls sh_i2c_read(), but read length is 0. So acutally it does not read device at all. This patch prepares dummy buffer and read data into it.
Signed-off-by: Tetsuyuki Kobayashi
Acked-by: Heiko Schocher
Signed-off-by: Nobuhiro Iwamatsu
08 Apr, 2014
1 commit
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Conflicts:
arch/arm/cpu/arm926ejs/mxs/Makefile
include/configs/trats.h
include/configs/trats2.h
include/mmc.h
04 Apr, 2014
1 commit
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Conflicts:
arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg
arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfgSigned-off-by: Stefano Babic
03 Apr, 2014
1 commit
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Commit 2faf5fb82ed6 introduced a regression that causes a data
abort when running scsi init followed by scsi reset.There are 2 problems with the original commit
1) ALLOC_CACHE_ALIGN_BUFFER() allocates memory on the stack but is
assigned to ataid[port] and used by other functions.
2) The function ata_scsiop_inquiry() tries to free memory which was
never allocated on the heap.Fix these problems by using tmpid as a temporary cache aligned buffer.
Allocate memory separately for ataid[port] and re-use it if required.Fixes: 2faf5fb82ed6 (ahci: Fix cache align error messages)
Reported-by: Eli Nidam
Signed-off-by: Roger Quadros
02 Apr, 2014
5 commits
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1. The Data timeout counter value in eSDHC_SYSCTL register is
not working as it should be, so add quirks to enable this
workaround to fix it to the max value 0xE.2. Add CONFIG_SYS_FSL_ERRATUM_ESDHC111 to enable its workaround.
* Update of patch for change mmc interface by
Pantelis AntoniouSigned-off-by: Haijun Zhang
Acked-by: Pantelis Antoniou -
The controller reset is performed now if command error occurs.
This commit adds the reset for the case of data related errors too.Signed-off-by: Andrew Gabbasov
Acked-by: Pantelis Antoniou -
Calculation of the timeout value should be based on actual clock value,
written to controller registers. Since mmc->tran_speed is either the
maximum allowed speed, or the preliminary value, that is be not yet
set to registers, the actual timeout, taken by the controller, based
on its clock settings, may be much longer than expected, based on
mmc->tran_speed value. In particular it happens at early initialization
stage, when typical value of mmc->tran_speed is 20MHz or 26MHz, while
actual clock setting, configured in the controller, is 400kHz.
It's more correct to use mmc->clock value for timeout calculation instead.Signed-off-by: Andrew Gabbasov
Acked-by: Pantelis Antoniou -
Some eMMC chips may need the RST_n_FUNCTION bit set to a non-zero value
in order for warm reset of the system to work. Details on this being
required will be part of the eMMC datasheet. Also add using this
command to the dra7xx README.* Whitespace fix by panto
Signed-off-by: Tom Rini
Acked-by: Pantelis Antoniou -
Signed-off-by: Nobuhiro Iwamatsu
Reported-by: Masahiro Yamada
Acked-by: Pantelis Antoniou
