02 Dec, 2014
1 commit
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Enable GIS function on imx6sx SDB uboot.
Expand CONFIG_SYS_MALLOC_LEN to 16M.Signed-off-by: Sandor Yu
(cherry picked from commit add90339c4e0ac9630f3c2a34d46b4f60265f56f)
30 Nov, 2014
2 commits
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We use PFUZE200 for SX SDB RevB board and PFUZE100 for SX SDB RevA board.
Show correct msg according DeviceID, since PFUZE200 and PFUZE100 have different
DeviceID. PFUZE200's id is 1, while PFUZE100's is 0.Signed-off-by: Peng Fan
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kernel and dtb file location should be changed from 0x1000000 and
0x2000000 to 0x4000000 and 0x5000000, since the uboot partition expanded
to 64M.Signed-off-by: Allen Xu
(cherry picked from commit eb4e6a6e65fe9074095869ecd5ccfe0a1559917d)
24 Nov, 2014
1 commit
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According to RM, there is 16bytes between offset ana1 and offset ana2.
So should add 3 int hole 'u32 reserved[3]' between ana1 and ana2.Also add the reserved bytes for ana2 in this patch.
Signed-off-by: Peng Fan
(cherry picked from commit b0fd5f272895dfb0891872c099df7eef1519f729)
23 Nov, 2014
1 commit
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Expand the uboot space to 64m to reserve enough space for FCB, DBBT and
u-boot.Signed-off-by: Allen Xu
(cherry picked from commit 54b3f6ba9097f4ed4cc8953a806c872444875a29)
21 Nov, 2014
1 commit
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Current uboot does not support bmode sd3. So add this to make
'bmode sd3' command in uboot can work fine.Signed-off-by: Peng Fan
(cherry picked from commit 8f9c61e391687f9ef6e1f735040bd0d679320215)
16 Nov, 2014
2 commits
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Modified the mtd index for imx6 sabreauto board, split the parallel nor
to two partitions and the NAND index could be align with imx6sx board for
mfgtool download.Signed-off-by: Allen Xu
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On imx6sx sabreauto, both QSPI1 and NAND would be mapped as mtd devices,
since we have already set the kernel to load QSPI1 first, the mtd index
for NAND need to be changed.Signed-off-by: Allen Xu
12 Nov, 2014
1 commit
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Add 14x14 arm2 nand support
Signed-off-by: Frank Li
11 Nov, 2014
2 commits
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Since we use WDOG_B reset now, we have to clear WDOG3 Power Down Enable
bit to avoid system reboot during normal kernel boot.
For mx6sxsabresd board, we have to make sure pad setting for WDOG_B ready
before mux ready, otherwise also cause reboot. But that dependes on hardware
design, only need on mx6sxsabresd board.Signed-off-by: Robin Gong
(cherry picked from commit 26875f93ac7e84748fa63e5f0dd948d12e663e43) -
Changed the QSPI PAD setting, the previous output drive strength is too
strong.Signed-off-by: Allen Xu
(cherry picked from commit 9dfb4a5ee01740eadb751ca5c9edfbec6f5059e3)
06 Nov, 2014
1 commit
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MX6SX sabreauto board has analog video input from VADC. Add the GIS
support for this board that video input can display on LVDS at booting.The environment variable "gis" must be set to "vadc" to enable the function.
Signed-off-by: Ye.Li
(cherry picked from commit 5f2008a6dc08f07d462a063a0642f5e54fedbd21)
24 Oct, 2014
3 commits
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Since the qspi2_clk_root is the root clock of u_gpmi_bch_input_gpmi_io_clk,
before switching the parent of qspi2_clk_root, we must gate off it.Signed-off-by: Ye.Li
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For NAND boot, the kernel zImage and rootfs also need to load from
NAND. Add the environment variables for this.Signed-off-by: Ye.Li
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Fix the GPIO assignments as per the board schematics.
Signed-off-by: Richard Zhu
23 Oct, 2014
1 commit
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supported NAND boot on 19x19 ARM2 board.
Signed-off-by: Allen Xu
22 Oct, 2014
1 commit
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The bootdata.size should contain the IVT offset part, but the calculation
for bootdata.size in imximage tool does not. This will cause some data at
the end of image not be loaded into memory.Signed-off-by: Ye.Li
20 Oct, 2014
3 commits
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The MAX7322 will fail to work on 19x19 arm2 revB board. This failure
is caused by the MAX7322 reset pin is not released when calling the
setup_fec function.The MAX7322 reset pin is same as PHY reset pin. This patch fixes the issue
by moving the PHY reset from setup_iomux_fec1 to setup_fec.Signed-off-by: Ye.Li
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The MAX7310 uses I2C3 bus. At system initialization, enable the driver to:
1. Reset CPU_PER_RST_B signal
2. Set the steering for ENET
3. Enable the LVDS displaySigned-off-by: Ye.Li
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When set the pinmux to I2C functionality, the SION is required to enabled.
Signed-off-by: Ye.Li
11 Oct, 2014
1 commit
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The PHY reset on 19x19 arm2 board is GPIO6_18, not GPIO4_22.
This causes the ethernet phy failed to work.Signed-off-by: Ye.Li
09 Oct, 2014
4 commits
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Add android fastboot, recovery and booti support for mx6sx sabreauto board.
Signed-off-by: Ye.Li
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Set the correct bmode value for booting from SDA/SDB/QSPI1/NAND
Signed-off-by: Ye.Li
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define CONFIG_SPI_FLASH_BAR in mx6sx_arm2.h mx6sxsabreauto.h to
enable access to flash array higher than 16MB.CONFIG_SPI_FLASH_BAR is also set in mx6sxsabresd.h for RevB board.
Actually, if QSPI flash size
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By introducing CONFIG_SPI_FLASH_BAR and add related command in LUT to
enable fsl_qspi.c can handle flash size bigger that 16M. Because uboot
does not support 32bits address access, this means bank address should
be used to access bigger flash.It is hard to let qspi driver dynamically set LUT, so BRRD BRWR RDEAR
and WREAR are all supported.Signed-off-by: Peng Fan
08 Oct, 2014
1 commit
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OPCODE_BE_4K is supported. To qspi flashes which support 4k sector
erase, spi framework will use OPCODE_BE_4K command. Thus add this
support to let uboot can erase such qspi flashes.Signed-off-by: Peng Fan
30 Sep, 2014
1 commit
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enable ldo-bypass check on all mx6sxsabresd boards.
Signed-off-by: Robin Gong
29 Sep, 2014
1 commit
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The mx6sx sabreauto boards uses 2G DDR3. Modify the configuration
PHYS_SDRAM_SIZE to this size.Signed-off-by: Ye.Li
Acked-by: Jason Liu
26 Sep, 2014
2 commits
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Create mx6sx sabreauto BSP file and configurations. The devices below
have been supported:1. SD/MMC/eMMC on SDA/SDB (base board) sockets
2. USB OTG port and USB HOST port (base board)
3. NAND flash
4. QuadSPI flash on QSPI1
5. I2C
6. PMIC PFUZE100
7. Onboard ethernet chip on ENET2
8. Splash screen on LVDSSigned-off-by: Ye.Li
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Add support for i.MX6SX 14x14 lpddr2 arm2 board, same
as 17x17 arm2 except lpddr2 instead of ddr3.Signed-off-by: Nitin Garg
25 Sep, 2014
1 commit
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Currently, flash quad bit is set in "spi_flash_validate_params" and later
at the end in the same api, we write 0 to status register for few flashes,
thereby overriding the quad bit set. This fix moves the quad bit setting
outside this api in "spi_flash_probe_slave"Signed-off-by: Sourav Poddar
Reviewed-by: Jagannadha Sutradharudu Teki
23 Sep, 2014
1 commit
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ROM fixes the WEIM plugin issue in TO 1.2. The work around for hacking WEIM base
address to ROM variable is not needed. To avoid hacking useful data, remove the
work around for TO 1.2 and higher revisions.Signed-off-by: Ye.Li
18 Sep, 2014
6 commits
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As M4 is sourcing UART clk from OSC, to make UART work
when M4 is enabled, need to select OSC as clk parent,
24M OSC is enough for debug UART in uboot.Signed-off-by: Anson Huang
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Set the CONFIG_MXC_GPT_HCLK configuration in mx6_common.h, so that
enable the 24Mhz OSC GPT on all MX6 platforms.Signed-off-by: Ye.Li
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For MX6SL, uses the OSC 24Mhz as the preclk source in CCM. Align the
preclk setting with kernel.Signed-off-by: Ye.Li
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For MX6SL and MX6SX, the perclk can come from OSC 24Mhz source. Fix
the get_ipg_per_clk function to support it.Signed-off-by: Ye.Li
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The MX6SL has the perclk_clk_sel to select the perclk source. Add
its define in CCMSigned-off-by: Ye.Li
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Introduce a new configuration "CONFIG_MXC_GPT_HCLK". When it is set,
the GPT will use 24Mhz OSC as clock source. Otherwise, the GPT will
use 32Khz OSC as clock source.Since only the GPT on iMX6 series provide the clock source option for
24Mhz OSC. For other series(MX5), if the configuration is set, the
perclk will be selected as clock source.MX6Q/D Rev 1.0 and MX6SL can't use the 24Mhz OSC clock source option,
so select the perclk for them. For MX6SL, we will set the OSC 24Mhz to
perclk in CCM, so eventually the clock comes from OSC 24Mhz.Signed-off-by: Ye.Li
11 Sep, 2014
1 commit
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The self-bias circuit is used by the bandgap during startup.
Once the bandgap has stabilized, the self-bias circuit should be
disabled for best noise performance of analog blocks.
Also this bit should be disabled before the chip enters STOP mode or
when ever the regular bandgap is disabled.Signed-off-by: Ranjani Vaidyanathan
10 Sep, 2014
1 commit
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THe anatop registers structure is duplicated with CCM structure at
PLL fields.
Since we are suggested not to use the name "anatop" any longer, merge
the anatop registers to the CCM structure "mxc_ccm_reg" and use CCM
to replace anatop.Signed-off-by: Ye.Li