21 Nov, 2014
1 commit
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Current uboot does not support bmode sd3. So add this to make
'bmode sd3' command in uboot can work fine.Signed-off-by: Peng Fan
(cherry picked from commit 8f9c61e391687f9ef6e1f735040bd0d679320215)
11 Nov, 2014
2 commits
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Since we use WDOG_B reset now, we have to clear WDOG3 Power Down Enable
bit to avoid system reboot during normal kernel boot.
For mx6sxsabresd board, we have to make sure pad setting for WDOG_B ready
before mux ready, otherwise also cause reboot. But that dependes on hardware
design, only need on mx6sxsabresd board.Signed-off-by: Robin Gong
(cherry picked from commit 26875f93ac7e84748fa63e5f0dd948d12e663e43) -
Changed the QSPI PAD setting, the previous output drive strength is too
strong.Signed-off-by: Allen Xu
(cherry picked from commit 9dfb4a5ee01740eadb751ca5c9edfbec6f5059e3)
24 Oct, 2014
1 commit
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Since the qspi2_clk_root is the root clock of u_gpmi_bch_input_gpmi_io_clk,
before switching the parent of qspi2_clk_root, we must gate off it.Signed-off-by: Ye.Li
20 Oct, 2014
2 commits
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The MAX7322 will fail to work on 19x19 arm2 revB board. This failure
is caused by the MAX7322 reset pin is not released when calling the
setup_fec function.The MAX7322 reset pin is same as PHY reset pin. This patch fixes the issue
by moving the PHY reset from setup_iomux_fec1 to setup_fec.Signed-off-by: Ye.Li
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The MAX7310 uses I2C3 bus. At system initialization, enable the driver to:
1. Reset CPU_PER_RST_B signal
2. Set the steering for ENET
3. Enable the LVDS displaySigned-off-by: Ye.Li
11 Oct, 2014
1 commit
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The PHY reset on 19x19 arm2 board is GPIO6_18, not GPIO4_22.
This causes the ethernet phy failed to work.Signed-off-by: Ye.Li
09 Oct, 2014
2 commits
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Add android fastboot, recovery and booti support for mx6sx sabreauto board.
Signed-off-by: Ye.Li
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Set the correct bmode value for booting from SDA/SDB/QSPI1/NAND
Signed-off-by: Ye.Li
30 Sep, 2014
1 commit
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enable ldo-bypass check on all mx6sxsabresd boards.
Signed-off-by: Robin Gong
26 Sep, 2014
2 commits
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Create mx6sx sabreauto BSP file and configurations. The devices below
have been supported:1. SD/MMC/eMMC on SDA/SDB (base board) sockets
2. USB OTG port and USB HOST port (base board)
3. NAND flash
4. QuadSPI flash on QSPI1
5. I2C
6. PMIC PFUZE100
7. Onboard ethernet chip on ENET2
8. Splash screen on LVDSSigned-off-by: Ye.Li
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Add support for i.MX6SX 14x14 lpddr2 arm2 board, same
as 17x17 arm2 except lpddr2 instead of ddr3.Signed-off-by: Nitin Garg
10 Sep, 2014
1 commit
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THe anatop registers structure is duplicated with CCM structure at
PLL fields.
Since we are suggested not to use the name "anatop" any longer, merge
the anatop registers to the CCM structure "mxc_ccm_reg" and use CCM
to replace anatop.Signed-off-by: Ye.Li
04 Sep, 2014
1 commit
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Couple of issues in commit 21a2eb5f. The RAM size is wrong and
max number of DCD is 220.Signed-off-by: Nitin Garg
29 Aug, 2014
1 commit
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Add support for i.MX6DQ/DL arm2 LPDDR2 boards.
Signed-off-by: Nitin Garg
26 Aug, 2014
2 commits
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In ldo-bypass mode, we need trigger WDOG_B pin to reset pmic in ldo-bypass mode.
Signed-off-by: Robin Gong
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Current only set VDDARM_IN@1.175V/VDDSOC_IN@1.175V before ldo bypass switch.
So untile ldo bypass switch happened, these voltage setting is set in ldo-enable
mode. But in datasheet, we need 1.15V + 125mV = 1.275V for VDDARM_IN. We need
to downgrade cpufreq to 400Mhz and restore after ldo bypass mode switch.Signed-off-by: Robin Gong
08 Aug, 2014
1 commit
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Correct the wrong setting, otherwise, i2c recovery code will use
the wrong scl pin to recove, and will never recovery successfully.Signed-off-by: Robin Gong
07 Aug, 2014
2 commits
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The BOOTCFG value used by bmode for SABRESD eMMC are actually for SD card.
Fixed the value to correct one.Signed-off-by: Ye.Li
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HWApps team updates iMX6SX 19x19 validation board LPDDR2 script.
This script is JEDEC compliant.
http://compass.freescale.net/livelink/livelink/open/232537085Update the LPDDR2 settings in DCD and plugin.
Signed-off-by: Ye.Li
01 Jul, 2014
1 commit
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Align the keymap with Android rootfs as:
FUNC1 -- > Volume +
FUNC2 -- > Volume -Signed-off-by: guoyin.chen
30 Jun, 2014
1 commit
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The kernel changes to fix the mmcblk index with USDHC controllers
as below:
mmcblk0 ---> USDHC1
mmcblk1 ---> USDHC2
mmcblk2 ---> USDHC3
mmcblk3 ---> USDHC4So in u-boot, the "mmcroot" must be updated together.
When booting from SD/MMC device, change the "mmcroot" to
dynamically set according to the boot USDHC controller.
It is the same mechanism as "mmcdev" used for kernel image loading.
Therefore, the uboot, kernel image, dtb and rootfs are required
in same SD/MMC card.
To disable the mmc dynamical detection, set the "mmcautodetect" to "no",
then "mmcroot" and "mmcdev" will not be overwritten.When booting from other devices which needs to load kernel, dtb and
rootfs from SD/MMC card, their "mmcdev" reset vaule is
CONFIG_SYS_MMC_ENV_DEV and "mmcroot" reset value is CONFIG_MMCROOT.Signed-off-by: Ye.Li
29 Jun, 2014
1 commit
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Update latest DDR3 scirpts for imx6sx SabreSD and 19x19 DDR3 ARM2 board
as provided by board team.
(http://sw-git.freescale.net/cgi-bin/gitweb.cgi?p=ddr-scripts-rel.git)Signed-off-by: Ye.Li
25 Jun, 2014
1 commit
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The NOR flash PC28F00AG18 has 512 of 256KB erase blocks which are
locked after power on reset. Change the 17x17 ARM2 configurations
to match the flash parameters, and enable the CONFIG_SYS_FLASH_PROTECTION
to allow write to the flash.The EIM-NOR on 17x17 ARM2 board uses MUXed mode. This has less
effort on board rework.When boot from EIM-NOR, set SW8, SW7, SW5 to all off.
Signed-off-by: Ye.Li
20 Jun, 2014
1 commit
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Currently, kernel common regulator framework can't support setting pmic mode
by common DTS, so move the related code to u-boot firstly.Signed-off-by: Robin Gong
18 Jun, 2014
1 commit
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When enabling "CONFIG_SECURE_BOOT", the build broken on iMX6SX platform
due to two problems.1. The imximage tool in v2014 changes the command name of "SECURE_BOOT"
to "CSF". Must update it in imximage.cfg scripts.2. The iMX6SX uses "CONFIG_ROM_UNIFIED_SECTIONS", but some HAB API
definitions are not defined and cause compile errors.
(HAB_RVT_REPORT_EVENT_NEW, HAB_RVT_REPORT_STATUS_NEW,
HAB_RVT_AUTHENTICATE_IMAGE_NEW, HAB_RVT_ENTRY_NEW, HAB_RVT_EXIT_NEW)Signed-off-by: Ye.Li
17 Jun, 2014
14 commits
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The eMMC chip on iMX6SX SABRESD board is DNP at default. HW rework is
needed to weld it on the eMMC socket and disconnect SD card slot.The pins IOMUX of eMMC are different with SD card slot:
1. The eMMC uses 8 data pins, while SD card slot only uses 4 bits.
2. The CD pin used by SD card slot works as a data pin for eMMC.So adding a new u-boot target "mx6sxsabresd_emmc" for the eMMC support,
rather than using the SD boot configuration.Signed-off-by: Ye.Li
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add clear print log to show pfuze200 or pfuze100 found on mx6qsabresd/
mx6slevk/mx6sx_19x19_arm2 boards.Signed-off-by: Robin Gong
Signed-off-by: Ye.Li -
Enable the "CONFIG_CMD_BMODE" and add BSP support.
"bmode" supports to reboot:
SD4, QSPI2 (SABRESD)
SD2, SD3, eMMC, QSPI2, NAND, SPINOR (17x17 ARM2)
SD1, QSPI2, SPINOR, EIMNOR (19x19 ARM2)BTW: Board rework is needed on ARM2 for NAND, SPINOR or EIMNOR boot.
Signed-off-by: Ye.Li
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Enable the video drivers and MXS LCDIF driver to support the
splash screen on MX6SX SDB and 19x19 ARM2. Add BSP codes for video
parameters and LCDIF/LVDS initialization."panel" env is used for selecting the display panel.
Set "panel" env to "Hannstar-XGA" for LVDS display.
Set "panel" env to "MCIMX28LCD" for parallel LCD display.Signed-off-by: Ye.Li
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Update NAND memory layout for match with new mfg tool.
Signed-off-by: Ke Qinghua
Signed-off-by: Ye.Li -
Add BSP codes to mx6sxsabresd to support android uboot features:
fastboot, booti and recoverySigned-off-by: Ye.Li
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T support M4 boot in 50 ms, kick start M4 at "board_early_init_f"
stage where u-boot passes ARM and architecture initialization.Add a configuration "CONFIG_SYS_AUXCORE_FASTUP" for this feature
enablement. And a build config "mx6sxsabresd_m4fastup".
Adjust the default M4 image address to 0x78000000 represented by
"CONFIG_SYS_AUXCORE_BOOTDATA".When M4 fast boot is enabled, RDC should be enabled together and
the QSPI driver must turn off, because M4 is running on QSPI flash
in XIP. Setup this relationship by configurations.Signed-off-by: Ye.Li
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According to the SRS, in the M4 CAN demo, the GPIO group1 will be
shared between A9 and M4. At A9 side, the pins 0, 1, 2, 3 are used.
M4 also uses one pin in its application.To synchronize the registers setttings of GPIO1, must enable RDC
and RDC semaphore on the GPIO1.Signed-off-by: Ye.Li
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Add BSP codes for iMX6SX SABRE SD board to support SD/MMC,
USB, QSPI2 NOR Flash, Ethernet, I2C, PMIC and
M4 command boot(bootaux).Add board build targets of SABER SD for boot device:
mx6sxsabresd --- SD/MMC
mx6sxsabresd_qspi2 --- QuadSPI2 NOR flashSigned-off-by: Ye.Li
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Add script "imximage_lpddr2.cfg" for DDR controller settings of LPDDR2.
Modify "plugin.S" for LPDDR2.
Add build target for 19x19 LPDDR2 ARM2 board.Signed-off-by: Ye.Li
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Add BSP codes for iMX6SX 19x19 DDR3 ARM2 board to support SD/MMC,
USB, QSPI2 NOR Flash, SPI NOR flash, WEIM NOR Flash, Ethernet,
I2C, PMIC and M4 command boot(bootaux).Some features has conflicts, so can't be enabled at same time:
WEIM-NOR QSPI pin conflict
QSPI SPI-NOR u-boot driver conflict
SPI-NOR SD2 pin conflictAdd board build targets of 19x19 DDR3 ARM2 for boot device:
mx6sx_19x19_ddr3_arm2 --- SD/MMC/eMMC
mx6sx_19x19_ddr3_arm2_spinor --- SPINOR on ECSPI4 CS0
mx6sx_19x19_ddr3_arm2_eimnor --- WEIM NOR flash
mx6sx_19x19_ddr3_arm2_qspi2 --- QuadSPI2 NOR flashSigned-off-by: Ye.Li
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Add BSP codes for iMX6SX 17x17 ARM2 board to support SD/MMC,
USB, QSPI2 NOR Flash, SPI NOR flash, NAND Flash, Ethernet, I2C
,PMIC and M4 command boot (bootaux).Some features has conflicts, so can't be enabled at same time:
QSPI NAND pin conflict
QSPI SPI-NOR u-boot driver conflict
SPI-NOR SD2 pin conflictAdd board build targets of 17x17 ARM2 for boot device:
mx6sx_17x17_arm2 --- SD/MMC/eMMC
mx6sx_17x17_arm2_spinor --- SPINOR on ECSPI4 CS0
mx6sx_17x17_arm2_nand --- NAND flash
mx6sx_17x17_arm2_qspi2 --- QuadSPI2 NOR flashSigned-off-by: Ye.Li
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iMX6SX has different enet system clocks with iMX6SL, and has two ENET
controllers. So update clocks and soc APIs accordingly to support this
features.1. Modify the clock API "enable_enet_clock" to enable enet system clock
for enet controllers.
2. Enet RGMII TX clock source may come from external or internal PLL.
By default, use the external phy CLK_25M output as TX clock source.
When using internal PLL as source, the function enable_fec_anatop_clock
must be called to enable clock for each enet controller.
3. Modify the MAC address function "imx_get_mac_from_fuse" to get either
ENET MAC address.
4. Add configuration "CONFIG_FEC_MXC_25M_REF_CLK" to enable ENET 25Mhz
reference clock.
5. Modify imx6slevk BSP to fit the new APIs.Signed-off-by: Fugang Duan
Signed-off-by: Ye.Li -
Sabreauto board has pin conflict (pin EIM_D18) between NOR flash
and i2c3. To enable the USB host, the i2c3 must be used to operate
the max7310 IO expander to output the VBUS power.As SPINOR is enabled at default, it is impossible to use USB host
at same time. Thus, remove the SYS_USE_SPINOR from sabreauto
configurations to disable SPINOR.Signed-off-by: Ye.Li