27 Apr, 2020
3 commits
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Add flexspi_nand driver which works on iMX flexspi controller to support
SPI NAND flash. This driver requires DM_SPI and follows SPI-MEM interfaces
to adapt to the SPI NAND framework.Note: Current implementation limits to the 12-bit column address. This is
popular in main stream SPI NAND and flash devices supported in u-boot.
If device with larger page size (> 4096) needs to support, we have to change
the driver.Signed-off-by: Ye Li
(cherry picked from commit d5c2580a245fa0cd4ae0012ceb5c8bd2f497f19c) -
Add the fuse checking in drivers, when the module is disabled in fuse,
the driver will not work.Changed drivers: BEE, GPMI, APBH-DMA, ESDHC, FEC, QSPI, ECSPI, I2C,
USB-EHCI, GIS, LCDIF and EPDC.Signed-off-by: Ye Li
(cherry picked from commit 1704e116f9b39aeb99201919a18bc2b1e19a980e)
(cherry picked from commit 2d3b5df8530cd5ef883750378838dea7c40259af)
(cherry picked from commit 6e8c9ae136bee8ec0121c1db4b935510caad09db)
(cherry picked from commit 99b54a6965904a879afdb6883a519de726cb4e96) -
support to read the flag status in driver to avoid the spi-nor framework
wait_for_ready hang issue.Signed-off-by: Han Xu
(cherry picked from commit 767faa948d2d140b6d56ee505f81f8f57c045a3d)
(cherry picked from commit 55e83ccb588c3e953f55148161bc524b5dab7a25)
(cherry picked from commit 92b281f91792ffc76e9541fa341d6f46c6ec2b7a)
23 Apr, 2020
1 commit
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Port fsl_fspi driver for flexspi controller from imx_v2019.04.
This driver supports:
1. DDR Quad output
2. Prefetch function for improve read performance.
3. Fast read and Quad read for one line read mode.
4. Read flash FSR register.
5. DM driver and SPI-MEM supportedSigned-off-by: Han Xu
Signed-off-by: Ye Li
(cherry picked from commit ae4e80b7b0debd2ad868781aaeb28ca4f2d9a8aa)
(cherry picked from commit dcd5504f6493d9aed415f397f1c13611fc202605)
(cherry picked from commit 902fba8f72e98d6c742674d305c855f3595c48b6)
04 Apr, 2020
1 commit
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- Add support for Jetson Nano, plus miscellaneous other fixes found
during Nano bringup.
- Add Igor's update_uboot wrapper patches.
03 Apr, 2020
3 commits
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This Tegra QSPI driver hadn't been brought up to date with how
DM drivers are fetching data from the FDT now, and was pulling
in bogus data for base, max freq, etc. Fixed ofdata_to_platdata
to work the same way it does in the tegra114 SPI driver, using
dev_read_ functions.Signed-off-by: Tom Warren
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When claim_bus was setting the clock, it reset the QSPI controller,
which wipes out any tap delays set by previous bootloaders (nvtboot,
CBoot for example on Nano). Instead of doing that in claim_bus, which
gets called a lot, moved clock setting to probe(), and set tap delays
there, too. Also updated clock to 80MHz to match CBoot. Now QSPI env
save works reliably again.Signed-off-by: Tom Warren
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claim_bus() is passed a udevice *dev, which is the bus device's parent.
In this driver, claim_bus assumed it was the bus, which caused the
'priv' info pointer to be wrong, and periph_id was incorrect. This in
turn caused the periph clock call to assign the wrong clock (PLLM
instead of PLLP0), which caused a kernel warning. I only saw the 'bad'
periph_id when enabling DEBUG due to an assert. Not sure how QSPI was
working w/this errant clock, but it was moot as QSPI wasn't active
unless you probed it, and that wasn't happening until I posted a patch
to enable env save to QSPI for Nano (coming soon).Signed-off-by: Tom Warren
02 Apr, 2020
2 commits
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This feature should not be enabled in release but can be useful for
developers who need to monitor register accesses at some specific places.Helped me identify a bug in u-boot, by comparing the register accesses
from the u-boot driver with the ones from its linux variant.Signed-off-by: Tudor Ambarus
[jagan: use 16 bit array with tmp variable]
Signed-off-by: Jagan Teki
Reviewed-by: Jagan Teki -
The sama5d2 QSPI controller memory space is limited to 128MB:
0x9000_00000-0x9800_00000/0XD000_0000--0XD800_0000.There are nor flashes that are bigger in size than the memory size
supported by the controller: Micron MT25QL02G (256 MB).Check if the address exceeds the MMIO window size. An improvement
would be to add support for regular SPI mode and fall back to it
when the flash memories overrun the controller's memory space.Fixes: 24c8ff4684c5 ("spi: Add Atmel QuadSPI driver")
Signed-off-by: Tudor Ambarus
Reviewed-by: Jagan Teki
31 Mar, 2020
3 commits
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Not all boards have the same CSB frequency, nor do every SPI slave
necessarily support running at 16.7 MHz. So implement ->set_speed;
that also allows using a smaller PM (i.e., 0) for slaves that do
support a higher speed.Based on work by Klaus H. Sørensen.
Cc: Klaus H. Sorensen
Signed-off-by: Rasmus Villemoes -
There are a few problems with the current driver.
First, it unconditionally reads from dout/writes to din whether or not
those pointers are NULL. So for example a simple "sf probe" ends up
writing four bytes at address 0:=> md.l 0x0 8
00000000: 45454545 45454545 05050505 05050505 EEEEEEEE........
00000010: 00000000 00000000 07070707 07070707 ................
=> sf probe 0
mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB53618 din 00000000 bitlen 8
mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 0FB536B8 bitlen 48
SF: Detected s25sl032p with page size 256 Bytes, erase size 64 KiB, total 4 MiB
=> md.l 0x0 8
00000000: ff000000 45454545 05050505 05050505 ....EEEE........
00000010: 00000000 00000000 07070707 07070707 ................(here I've change the first debug statement to a printf, and made it
print the din/dout pointers rather than the uints they point at).Second, as we can also see above, it always writes a full 32 bits,
even if a smaller amount was requested. So for example=> mw.l $loadaddr 0xaabbccdd 8
=> md.l $loadaddr 8
02000000: aabbccdd aabbccdd aabbccdd aabbccdd ................
02000010: aabbccdd aabbccdd aabbccdd aabbccdd ................
=> sf read $loadaddr 0x400 6
device 0 offset 0x400, size 0x6
mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB536E8 din 00000000 bitlen 40
mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 02000000 bitlen 48
SF: 6 bytes @ 0x400 Read: OK
=> sf read 0x02000010 0x400 8
device 0 offset 0x400, size 0x8
mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB53848 din 00000000 bitlen 40
mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 02000010 bitlen 64
SF: 8 bytes @ 0x400 Read: OK
=> md.l $loadaddr 8
02000000: 45454545 45450000 aabbccdd aabbccdd EEEEEE..........
02000010: 45454545 45454545 aabbccdd aabbccdd EEEEEEEE........Finally, when the bitlen is 24 mod 32 (e.g. requesting to read 3 or 7
bytes), the last three bytes and up being the wrong ones, since the
driver does a full 32 bit read and then shifts the wrong byte out:=> mw.l $loadaddr 0xaabbccdd 4
=> md.l $loadaddr 4
02000000: aabbccdd aabbccdd aabbccdd aabbccdd ................
=> sf read $loadaddr 0x444 10
device 0 offset 0x444, size 0x10
mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB536E8 din 00000000 bitlen 40
mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 02000000 bitlen 128
SF: 16 bytes @ 0x444 Read: OK
=> md.l $loadaddr 4
02000000: 552d426f 6f742032 3031392e 30342d30 U-Boot 2019.04-0
=> mw.l $loadaddr 0xaabbccdd 4
=> sf read $loadaddr 0x444 0xb
device 0 offset 0x444, size 0xb
mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB536E8 din 00000000 bitlen 40
mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 02000000 bitlen 88
SF: 11 bytes @ 0x444 Read: OK
=> md.l $loadaddr 4
02000000: 552d426f 6f742032 31392e00 aabbccdd U-Boot 219......Fix all of that by always using a character size of 8, and reject
transfers that are not a whole number of bytes. While it ends being
more work for the CPU, we're mostly bounded by the speed of the SPI
bus, and we avoid writing to the mode register in every loop.Based on work by Klaus H. Sørensen.
Cc: Klaus H. Sorensen
Signed-off-by: Rasmus Villemoes -
Currently, max_cs is write-only; it's just set in
mpc8xxx_spi_ofdata_to_platdata and not otherwise used.My mpc8309 was always resetting during an "sf probe 0". It turns out
dm_gpio_set_dir_flags() was being called with garbage, since nothing
had initialized priv->gpios[0] - our device tree used "cs-gpios"
rather than "gpios", so gpio_request_list_by_name() had returned 0.That would have been a lot easier to figure out if the chip select
index was sanity checked, so rename max_cs to cs_count, and reject a
xfer with a too large cs index.Signed-off-by: Rasmus Villemoes
06 Feb, 2020
3 commits
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Most files don't need this header and it pulls in quite of lots of stuff,
malloc() in particular. Drop it.Signed-off-by: Simon Glass
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At present dm/device.h includes the linux-compatible features. This
requires including linux/compat.h which in turn includes a lot of headers.
One of these is malloc.h which we thus end up including in every file in
U-Boot. Apart from the inefficiency of this, it is problematic for sandbox
which needs to use the system malloc() in some files.Move the compatibility features into a separate header file.
Signed-off-by: Simon Glass
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At present devres.h is included in all files that include dm.h but few
make use of it. Also this pulls in linux/compat which adds several more
headers. Drop the automatic inclusion and require files to include devres
themselves. This provides a good indication of which files use devres.Signed-off-by: Simon Glass
Reviewed-by: Anatolij Gustschin
04 Feb, 2020
1 commit
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When ich_spi_exec_op_hwseq() is called to erase a 4k block
(opcode = SPINOR_OP_BE_4K), it expects to find a length value in
op->data.nbytes, but that value is always 0. As a result, the while loop
is never executed and no erase is carried out.Fix this by dropping the loop code entirely, only keeping the relevant
parts of the loop body.See http://patchwork.ozlabs.org/patch/1222779/ for more detailed
background information and discussion.Signed-off-by: Wolfgang Wallner
Reviewed-by: Simon Glass
Signed-off-by: Bin Meng
28 Jan, 2020
9 commits
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TI's AM654 SoC has a Cadence OSPI IP. Add a new compatible string for
the same.Signed-off-by: Vignesh Raghavendra
Reviewed-by: Jagan Teki -
Cadence OSPI is similar to QSPI IP except that it supports Octal IO
(8 IO lines) flashes. Add support for Cadence OSPI IP with existing
driver using new compatibleSigned-off-by: Vignesh Raghavendra
Reviewed-by: Jagan Teki -
Add support for Octal flash devices. Octal flash devices use 8 IO lines
for data transfer. Currently only 1-1-8 Octal Read mode is supported.Signed-off-by: Vignesh Raghavendra
Reviewed-by: Jagan Teki -
Add support for Direct Access Controller mode of Cadence QSPI. This
allows MMIO access to SPI NOR flash providing better read performance.
Direct mode is only exercised if AHB window size is greater than 8MB.
Support for flash address remapping is also not supported at the moment
and can be added in future.For better performance, driver uses DMA to copy data from flash in
direct mode using dma_memcpy().Signed-off-by: Vignesh Raghavendra
Tested-by: Simon Goldschmidt
Acked-by: Jagan Teki -
Current Cadence QSPI driver has few limitations. It assumes all read
operations to be in Quad mode and thus does not support SFDP parsing.
Also, adding support for new mode such as Octal mode would not be
possible with current configuration. Therefore move the driver over to spi-mem
framework. This has added advantage that driver can be used to support
SPI NAND memories too.
Hence, move driver over to new spi-mem APIs.Please note that this gets rid of mode bit setting done when
CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to
that config option.Signed-off-by: Vignesh Raghavendra
Tested-by: Simon Goldschmidt
Acked-by: Jagan Teki -
Make sure corresponding setup registers are updated depending on CS.
This ensures that driver can support QSPI flashes on ChipSelects other
than on CS0Reported-by: Andreas Dannenberg
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Jagan Teki -
The SPI stack relies on a proper bus speed/mode configuration
by calling dm_spi_claim_bus(). However the hitherto code
allowed to accidentally override those settings in
the spi_get_bus_and_cs() routine.The initially established speed could be discarded by using
the slave platdata, which turned out to be an issue on
the platforms whose slave maximum supported frequency
is not on par with the maximum frequency of the bus controller.This patch fixes above issue by configuring the bus from
spi_get_bus_and_cs() only in case it was not done before.Signed-off-by: Marcin Wojtas
Reviewed-by: Simon Glass
Acked-by: Jagan Teki -
Add chip select number check in spi_find_chip_select().
Signed-off-by: Bin Meng
Tested-by: Jagan Teki # SoPine -
This is a port of the kernel's spi-nxp-fspi driver. It uses the new
spi-mem interface and does not expose the more generic spi-xfer
interface. The source was taken from the v5.3-rc3 tag.The port was straightforward:
- remove the interrupt handling and the completion by busy polling the
controller
- remove locks
- move the setup of the memory windows into claim_bus()
- move the setup of the speed into set_speed()
- port the device tree bindings from the original fspi_probe() to
ofdata_to_platdata()There were only some style change fixes, no change in any logic. For
example, there are busy loops where the return code is not handled
correctly, eg. only prints a warning with WARN_ON(). This port
intentionally left most functions unchanged to ease future bugfixes.This was tested on a custom LS1028A board. Because the LS1028A doesn't
have proper clock framework support, changing the clock speed was not
tested. This also means that it is not possible to change the SPI
speed on LS1028A for now (neither is it possible in the linux driver).Signed-off-by: Michael Walle
Reviewed-by: Jagan Teki
Tested-by: Kuldeep Singh
23 Jan, 2020
1 commit
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This IP is also used on some arm SoC, so we allow to
use it on arm bcm68360 too.Signed-off-by: Philippe Reynes
18 Jan, 2020
1 commit
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These three clock functions don't use driver model and should be migrated.
In the meantime, create a new file to hold them.Signed-off-by: Simon Glass
14 Jan, 2020
1 commit
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When two instances of AXI QSPI with flash are added and tested
simultaneously the spi driver operations are relocated twice.
As a result code is accessing addresses outside of RAM when
relocated second time which is causing a crash.Tested on Microblaze.
Similar change was done in past by:
commit f238b3f0fbc9 ("watchdog: dm: Support manual relocation for watchdogs")
commit 2588f2ddfd60 ("dm: sf: Add support for all targets which requires MANUAL_RELOC")
commit 1b4c2aa25bdf ("gpio: dm: Support manual relocation for gpio")Signed-off-by: Ashok Reddy Soma
Signed-off-by: Michal Simek
07 Jan, 2020
1 commit
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Bring in the following merges:
commit 8fbbec12f7d2c18f8883f3371cfca74a98b5dd87
Merge: 87f69f467a83 63618e71e89b
Author: Tom Rini
Date: Fri Jan 3 09:48:47 2020 -0500Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq into next
- updates and fixes on ls1028a, lx2, ls1046a, MC-DPSPARSER support
commit 87f69f467a8335b171c71bf217d2625d515acd7c
Merge: c0912f9bbfb2 4466b9970319
Author: Tom Rini
Date: Tue Dec 24 08:18:19 2019 -0500Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx into next
- Enable DM driver on ppc/km boards
- Enable DM_USB for some of NXP powerpc platforms: P5040, T4240, T208x,
T104x, P4080, P2041, P2020, P1020, P3041
- Some updates in mpc85xx-ddr driver, km boardscommit c0912f9bbfb26dd03d189953678691b799d35b6e
Merge: 533c9f5714bd a1d6dc3f8407
Author: Tom Rini
Date: Wed Dec 18 07:20:19 2019 -0500Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-x86 into next
- Various x86 common codes updated for TPL/SPL
- I2C designware driver updated for PCI
- ICH SPI driver updated to support Apollo Lake
- Add Intel FSP2 base support
- Intel Apollo Lake platform specific drivers support
- Add a new board Google Chromebook Coralcommit 533c9f5714bdba79dc6f2629284d4c1a08a611d1
Merge: 553cb0688782 033e18b47bd0
Author: Tom Rini
Date: Tue Dec 17 07:53:08 2019 -0500Merge tag '20191217-for-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2c into next
i2c: for next
- misc: i2c_eeprom:
Add partition support and add ability to query size
of eeprom device and partitions
- i2c common:
add support for offset overflow in to address and add
sandbox tests for it.commit 553cb06887825314e74a9bdac337467c77d1db88
Merge: f39abbbc531e b4f98b3b16ec
Author: Tom Rini
Date: Thu Dec 12 08:18:59 2019 -0500Merge tag 'dm-next-13dec19' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm into next
buildman improvements including toolchain environment feature
sandbox unicode support in serial
27 Dec, 2019
1 commit
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The Rockchip SPI controller's length register only supports 16-bits,
yielding a maximum length of 64KiB (the CTRLR1 register holds "length -
1"). Trying to transfer more than that (e.g., with a large SPI flash
read) will cause the driver to hang.Now, it seems that while theoretically we should be able to program
CTRLR1 with 0xffff, and get a 64KiB transfer, but that also seems to
cause the core to choke, so stick with a maximum of 64K - 1 bytes --
i.e., 0xffff.Note, that the size is further divided into 'minus 1' while writing
into CTRLR1.This change fixed two different read issues,
1. sf read failure when with > 0x10000
2. Boot from SPI flash failed during spi_flash_read call in
common/spl/spl_spi.cObserved and Tested in
- Rockpro64 with Gigadevice flash
- ROC-RK3399-PC with Winbond flashSigned-off-by: Jagan Teki
Reviewed-by: Kever Yang
15 Dec, 2019
9 commits
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Add support for Apollo Lake to the ICH driver. This involves adjusting the
mmio address and skipping setting of the bbar.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
In TPL we want to reduce code size and support running with CONFIG_PCI
disabled. Add special code to handle this using a fixed BAR programmed
into the SPI on boot. Also cache the SPI flash to speed up boot.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
Add this method so that the memory-mapped location of the SPI flash can
be queried.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
Apollo Lake (APL) only supports hardware sequencing. Add support for this
into the SPI driver, as an option.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
The Intel Fast SPI interface is similar to ICH. Add of-platdata support
for this using the "intel,fast-spi" compatible string.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
This incorrectly shortens read operations if there is a maximum write size
but no maximum read size. Fix it.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
It is useful to store the mmio base in platdata. It reduces the amount of
casting needed. Update the code and move the struct to the C file at the
same time, as we will need to use with of-platdata.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
Use debug() instead of printf() to reduce code size and change a bool
return value to the use the 'bool' type. Also drop the global data
declaration since it not actually used. Finally, set the log category.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
Move the header files into the right order.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng