15 Feb, 2018

1 commit


10 Feb, 2018

1 commit

  • To make this driver easier to be reused, dual-license DDR driver.

    Signed-off-by: York Sun
    CC: Simon Glass
    CC: Tom Rini
    CC: Heinrich Schuchardt
    CC: Thomas Schaefer
    CC: Masahiro Yamada
    CC: Robert P. J. Day
    CC: Alexander Merkle
    CC: Joakim Tjernlund
    CC: Curt Brune
    CC: Valentin Longchamp
    CC: Wolfgang Denk
    CC: Anatolij Gustschin
    CC: Ira W. Snyder
    CC: Marek Vasut
    CC: Kyle Moffett
    CC: Sebastien Carlier
    CC: Stefan Roese
    CC: Peter Tyser
    CC: Paul Gortmaker
    CC: Peter Tyser
    CC: Jean-Christophe PLAGNIOL-VILLARD

    York Sun
     

05 Jan, 2017

1 commit


06 Dec, 2016

1 commit

  • - add additional function erratum_a009942_check_cpo to check if the
    board needs tuning CPO calibration for optimal setting.
    - move ERRATUM_A009942(with revision to check cpo_sample option) from
    fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts.
    - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c
    - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942.

    Signed-off-by: Shengzhou Liu
    [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500]
    Reviewed-by: York Sun

    Shengzhou Liu
     

19 Jan, 2016

1 commit

  • In a number of places we had wordings of the GPL (or LGPL in a few
    cases) license text that were split in such a way that it wasn't caught
    previously. Convert all of these to the correct SPDX-License-Identifier
    tag.

    Signed-off-by: Tom Rini

    Tom Rini
     

01 Dec, 2015

1 commit


04 Aug, 2015

1 commit

  • By default the bstopre value has been set to 0x100, used to be 1/4
    value of refint. Modern DDR has increased the refresh time. Adjust
    to 1/4 of refresh interval dynamically. Individual board can still
    override this value in board ddr file, or to use auto-precharge.

    Signed-off-by: York Sun

    York Sun
     

21 Jul, 2015

1 commit


23 Apr, 2015

1 commit

  • Add/update registers for DDR4, including DQ mappings. Allow raw timing
    method used for all controllers. Update mode_9 register to 0x500 for
    improved stability. Check DDR controller version number individually
    in case a SoC has multiple DDR controllers of different versions.
    Increase read-write turnaround for DDR4 high speeds.

    Signed-off-by: York Sun

    York Sun
     

25 Feb, 2015

2 commits


24 Jan, 2015

1 commit


25 Sep, 2014

1 commit

  • U-boot has been initializing DDR for the main memory. The presumption
    is the memory stays as a big continuous block, either linear or
    interleaved. This change is to support putting some DDR controllers
    to separated space without counting into main memory. The standalone
    memory controller could use different number of DIMM slots.

    Signed-off-by: York Sun

    York Sun
     

23 Apr, 2014

1 commit


22 Feb, 2014

1 commit


26 Nov, 2013

1 commit