18 Apr, 2017

1 commit


29 Jan, 2016

6 commits


04 Aug, 2015

1 commit


09 Sep, 2014

3 commits

  • Remove the DMCTRL Tx snooping bits (TDSEN and TBDSEN) as a
    workaround for LS1. It has been observed that currently
    the Tx stops functioning after a fair amount of Tx traffic
    with these settings on. These bits are sticky and once set
    they cannot be reset from Linux, for instance.

    Signed-off-by: Claudiu Manoil

    Claudiu Manoil
     
  • This patch is to add etsec support for LS102xA. First, Little-endian
    descriptor mode should be enabled. So RxBDs and TxBDs are interpreted
    with little-endian byte ordering. Second, TSEC_SIZE and TSEC_MDIO_OFFSET
    are different from PowerPC, redefine them for LS1021xA.

    Signed-off-by: Alison Wang

    Alison Wang
     
  • fsl_enet.h defines the mapping of the usual MII management
    registers, which are included in the MDIO register block
    common to Freescale ethernet controllers. So it shouldn't
    depend on the CPU architecture but it should be actually
    part of the arch independent fsl_mdio.h.

    To remove the arch dependency, merge the content of
    asm/fsl_enet.h into fsl_mdio.h.
    Some files (like fm_eth.h) were simply including fsl_enet.h
    only for phy.h. These were updated to include phy.h instead.

    Signed-off-by: Claudiu Manoil

    Claudiu Manoil
     

23 Nov, 2013

4 commits

  • Use cross arch portable u32 instead of uint for the
    tsec registers. Remove the typedefs for the register
    struct definitions in the process. Fix long lines.

    Signed-off-by: Claudiu Manoil

    Claudiu Manoil
     
  • Currently, the buffer descriptor (BD) fields cannot be
    correctly accessed by a little endian processor. This
    patch fixes the issue by making the access of BDs to be
    portable among different cpu architectures.

    Use portable data types for the Rx/Tx buffer descriptor
    fields. Use portable I/O accessors to insure that the
    big endian BDs are correctly accessed by little endian
    cpus too, and to insure proper sync with the H/W.
    Removed the redundant RTXBD "volatile" type, as proper
    synchronization around BD data accesses is provided by
    the I/O accessors now.
    The "sparse" tool was also used to verify the correctness
    of these changes.

    Cc: Scott Wood

    Signed-off-by: Claudiu Manoil

    Claudiu Manoil
     
  • Fix bufPtr and the rxIdx/ txIdx occurrences to
    solve the related checkpatch warnings for the
    coming patches.

    Signed-off-by: Claudiu Manoil

    Claudiu Manoil
     
  • Remove tsec_t typedef. Define macros as getters of
    tsec and mdio register memory regions, for consistent
    initialization of various 'regs' fields and also to
    manage overly long initialization lines.
    Use the __iomem address space marker to address sparse
    warnings in tsec.c where IO accessors are used, like:

    tsec.c:394:19: warning: incorrect type in argument 1 (different
    address spaces)
    tsec.c:394:19: expected unsigned int volatile [noderef]
    *addr
    tsec.c:394:19: got unsigned int *
    [...]

    Add the __iomem address space marker for the tsec pointers
    to struct tsec_mii_mng memory mapped register regions.
    This solves the sparse warnings for mixig normal pointers
    with __iomem pointers for tsec.

    Signed-off-by: Claudiu Manoil

    Claudiu Manoil
     

29 Apr, 2011

1 commit

  • The tsec driver was defining the default MDIO address as
    the TSEC_BASE + 0x520, but on eTSEC2 controllers, the first
    TSEC's registers are separated from the MDIO registers. Use
    the existing MDIO_BASE_ADDR, instead.

    Signed-off-by: Andy Fleming
    Signed-off-by: Kumar Gala

    Andy Fleming
     

21 Apr, 2011

2 commits

  • This converts tsec to use the new PHY Lib. All of the old PHY support
    is ripped out. The old MDIO driver is split off, and placed in
    fsl_mdio.c. The initialization is modified to initialize the MDIO
    driver as well. The powerpc config file is modified to configure PHYLIB
    if TSEC_ENET is configured.

    Signed-off-by: Mingkai Hu
    Signed-off-by: Andy Fleming
    Signed-off-by: Kumar Gala
    Acked-by: Detlev Zundel

    Andy Fleming
     
  • Signed-off-by: Mingkai Hu
    Acked-by: Andy Fleming
    Signed-off-by: Kumar Gala
    Acked-by: Detlev Zundel

    Mingkai Hu
     

10 Jan, 2011

1 commit

  • The include/miiphy.h header duplicates a lot of things from linux/mii.h.
    So punt all the things that overlap to keep the API simple and to make
    merging between U-Boot and Linux simpler.

    Signed-off-by: Mike Frysinger

    Mike Frysinger
     

01 Feb, 2010

3 commits


06 Jan, 2010

2 commits

  • 1. Modified the tsec_mdio structure to include the new regs
    2. Modified the MDIO_BASE_ADDR so that it will handle both
    older version and new version of etsec.

    Signed-off-by: Sandeep Gopalpet
    Acked-by: Kim Phillips
    Signed-off-by: Kumar Gala

    Kumar Gala
     
  • Moved the mdio regs out of the tsec structure,and
    provided different offsets for tsec base and mdio
    base so that provision for etsec2.0 can be provided.

    This patch helps in providing the support for etsec2.0
    In etsec2.0, the MDIO register space and the etsec reg
    space are different.

    Also, moved the TSEC_BASE_ADDR and MDIO_BASE_ADDR definitons into
    platform specific files.

    Signed-off-by: Sandeep Gopalpet
    Acked-by: Kim Phillips
    Signed-off-by: Kumar Gala

    Sandeep Gopalpet
     

15 Jun, 2009

1 commit


13 Jun, 2009

1 commit


05 Dec, 2008

1 commit

  • This patch tries to ensure that phy interrupt pin
    won't be asserted after booting. We experienced
    following issues with current 88E1121R phy init:

    Marvell 88E1121R phy can be hardware-configured
    to share MDC/MDIO and interrupt pins for both ports
    P0 and P1 (e.g. as configured on socrates board).
    Port 0 interrupt pin will be shared by both ports
    in such configuration. After booting Linux and
    configuring eth0 interface, port 0 phy interrupts
    are enabled. After rebooting without proper eth0
    interface shutdown port 0 phy interrupts remain
    enabled so any change on port 0 (link status, etc.)
    cause assertion of the interrupt. Now booting Linux
    and configuring eth1 interface will cause permanent
    phy interrupt storm as the registered phy 1 interrupt
    handler doesn't acknowledge phy 0 interrupts. This
    of course should be fixed in Linux driver too.

    Signed-off-by: Anatolij Gustschin
    Acked-by: Andy Fleming
    Signed-off-by: Ben Warren

    Anatolij Gustschin
     

19 Oct, 2008

1 commit


13 Sep, 2008

1 commit


03 Sep, 2008

3 commits

  • Adds support for configuring the TBI to talk properly with the SerDes.

    Signed-off-by: Andy Fleming
    Signed-off-by: Ben Warren

    Andy Fleming
     
  • The tsec driver contains a hard-coded array of configuration information
    for the tsec ethernet controllers. We create a default function that works
    for most tsecs, and allow that to be overridden by board code. It creates
    an array of tsec_info structures, which are then parsed by the corresponding
    driver instance to determine configuration. Also, add regs, miiregs, and
    devname fields to the tsec_info structure, so that we don't need the kludgy
    "index" parameter.

    Signed-off-by: Andy Fleming
    Signed-off-by: Ben Warren

    Andy Fleming
     
  • This is to prepare the way for board code passing in the tsec_info structure

    Signed-off-by: Andy Fleming
    Signed-off-by: Ben Warren

    Andy Fleming