10 Apr, 2015
1 commit
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Reviewed-by: Jagannadha Sutradharudu Teki
Signed-off-by: Albert ARIBAUD (3ADEV)
06 Dec, 2014
2 commits
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This patch adds the driver for the Designware master SPI controller. This
IP core is integrated on the Altera SoCFPGA. This implementation is a
driver model (DM) implementation. So multiple SPI drivers can be used.
Thats necessary, since SoCFPGA also integrates the Cadence QSPI controller
used to connect the SPI NOR flashes. Without DM, using multiple SPI
drivers is not possible.This driver is very loosely based on the Linux driver. Most of the Linux
driver is removed. Only the polling loop for the transfer is really used
from this driver, as we don't support interrupts and DMA right now.This is tested on the SoCrates SoCFPGA board using the SPI pins on the
P14 header.Signed-off-by: Stefan Roese
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Vince Bridgers
Cc: Marek Vasut
Cc: Pavel Machek
Reviewed-by: Simon Glass
Cc: Jagannadha Sutradharudu Teki -
This driver is cloned from the Altera Rockerboard.org U-Boot
repository. I used this git tag: ACDS14.0.1_REL_GSRD_RC2. With Some
modification to support the U-Boot driver model (DM).As mentioned above, in this new version I ported this driver to the
new driver model (DM). One big advantage of this move is that now
multiple SPI drivers can be enabled on one platform. And since the
SoCFPGA also has the Designware SPI master controller integrated,
this feature is really needed to support both controllers.Because of this, this series needs the DT support for SoCFPGA
to be applied. For DT based probing in the SPI DM.Signed-off-by: Stefan Roese
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Vince Bridgers
Cc: Marek Vasut
Cc: Pavel Machek
Cc: Simon Glass
Cc: Jagannadha Sutradharudu Teki
23 Oct, 2014
5 commits
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This converts the Tegra SPI drivers to use driver model. This is tested
on:- Tegra20 - trimslice
- Tegra30 - beaver
- Tegra124 - dalmore(not tested on Tegra124)
Reviewed-by: Jagannadha Sutradharudu Teki
Signed-off-by: Simon Glass -
Add a new implementation of soft_spi that uses device tree to specify the
GPIOs. This will replace soft_spi_legacy for boards which use driver model.Signed-off-by: Simon Glass
Reviewed-by: Jagannadha Sutradharudu Teki -
Reserve the 'normal' name for use by driver model, and rename the old
driver so that it is clear that it is for 'legacy' drivers only.Signed-off-by: Simon Glass
Reviewed-by: Jagannadha Sutradharudu Teki -
U-Boot includes a SPI emulation driver already but it is not explicit, and
is hidden in the SPI flash code.Conceptually with sandbox's SPI implementation we have a layer which
creates SPI bus transitions and a layer which interprets them, currently
only for SPI flash. The latter is actually an emulation, and it should be
possible to add more than one emulation - not just SPI flash.Add a SPI emulation uclass so that other emulations can be plugged in to
support different types of emulated devices on difference buses/chip
selects.Signed-off-by: Simon Glass
Reviewed-by: Jagannadha Sutradharudu Teki -
Add a uclass which provides access to SPI buses and includes operations
required by SPI.For a time driver model will need to co-exist with the legacy SPI interface
so some parts of the header file are changed depending on which is in use.
The exports are adjusted also since some functions are not available with
driver model.Boards must define CONFIG_DM_SPI to use driver model for SPI.
Signed-off-by: Simon Glass
Reviewed-by: Jagannadha Sutradharudu Teki
(Discussed some follow-up comments which will address in future add-ons)
05 Jul, 2014
1 commit
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This patch returns back support for old ep93xx processors family
Signed-off-by: Sergey Kostanbaev
Cc: albert.u.boot@aribaud.net
09 Jun, 2014
1 commit
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Add Freescale QSPI driver support for VF610.
Signed-off-by: Alison Wang
Signed-off-by: Chao Fu
11 Jan, 2014
1 commit
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The Faraday FTSSP010 is a multi-function controller
which supports I2S/SPI/SSP/AC97/SPDIF. However This
patch implements only the SPI mode.NOTE:
The DMA and CS/Clock control logic has been altered
since hardware revision 1.19.0. So this patch
would first detects the revision id of the underlying
chip, and then switch to the corresponding software
control routines.Signed-off-by: Kuo-Jung Su
Signed-off-by: Jagannadha Sutradharudu Teki
CC: Tom Rini
19 Dec, 2013
1 commit
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This patch adds a driver for Renesas SoC's Quad SPI bus.
This supports with 8 bits per transfer to use with SPI flash.Signed-off-by: Kouei Abe
Signed-off-by: Nobuhiro Iwamatsu
Signed-off-by: Jagannadha Sutradharudu Teki
10 Dec, 2013
1 commit
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This adds a SPI framework for people to hook up simulated SPI clients.
Signed-off-by: Mike Frysinger
Signed-off-by: Simon Glass
01 Nov, 2013
1 commit
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Signed-off-by: Masahiro Yamada
07 Oct, 2013
1 commit
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Adds a SPI master driver for the TI QSPI peripheral.
- Added quad read support.
- Added memory mapped support.Signed-off-by: Matt Porter
Signed-off-by: Sourav Poddar
Signed-off-by: Jagannadha Sutradharudu Teki
07 Aug, 2013
1 commit
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Zynq spi controller driver supports 2 buses and
3 chipselects on each bus.Signed-off-by: Jagannadha Sutradharudu Teki
Acked-by: Siva Durga Prasad Paladugu
Signed-off-by: Michal Simek
24 Jul, 2013
1 commit
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Signed-off-by: Wolfgang Denk
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini
29 Mar, 2013
1 commit
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Conflicts:
drivers/spi/tegra20_sflash.c
include/fdtdec.h
lib/fdtdec.c
26 Mar, 2013
3 commits
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Add driver for tegra114 SPI controller. This controller is not
compatible with either the tegra20 or tegra30 controllers, so it
requires a new driver.Signed-off-by: Allen Martin
Signed-off-by: Tom Warren
Reviewed-by: Stephen Warren -
Add a common interface to fdt based SPI drivers. Each driver is
represented by a table entry in fdt_spi_drivers[]. If there are
multiple SPI drivers in the table, the first driver to return success
from spi_init() will be registered as the SPI driver.Signed-off-by: Allen Martin
Signed-off-by: Tom Warren
Reviewed-by: Stephen Warren -
Rename tegra SPI drivers to tegra20_flash and tegra20_slink in
preparation for commonization and addition of tegra114_spi.Signed-off-by: Allen Martin
Signed-off-by: Tom Warren
Reviewed-by: Stephen Warren
19 Mar, 2013
2 commits
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This supports Intel ICH7/9. The Intel controller is a little unusual in
that it is mostly intended for use with SPI flash, and has some
optimisations and features specifically for that application. In
particular it is not possible to support ongoing transactions that
continue over many calls with SPI_XFER_BEGIN and SPI_XFER_END.This driver supports writes of up to 64 bytes at a time, the limit
for the controller. Future work will improve this.Signed-off-by: Bernie Thompson
Signed-off-by: Duncan Laurie
Signed-off-by: Bill Richardson
Signed-off-by: Vadim Bendebury
Signed-off-by: Gabe Black
Signed-off-by: Simon Glass -
At present it is difficult to extend the SPI structure since all
drivers allocate it themselves, and few of them zero all fields. Add
a new function spi_alloc_slave() which can be used by SPI drivers
to perform this allocation, and thus ensure that all drivers can
better cope with SPI structure changes.Signed-off-by: Simon Glass
04 Mar, 2013
1 commit
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Spi driver for bf60x is different from old one, so implement a new
driver for it.Signed-off-by: Scott Jiang
Signed-off-by: Sonic Zhang
Signed-off-by: Bob Liu
Signed-off-by: Sonic Zhang
12 Feb, 2013
1 commit
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Add driver for tegra SPI "SLINK" style driver. This controller is
similar to the tegra20 SPI "SFLASH" controller. The difference is
that the SLINK controller is a genernal purpose SPI controller and the
SFLASH controller is special purpose and can only talk to FLASH
devices. In addition there are potentially many instances of an SLINK
controller on tegra and only a single instance of SFLASH. Tegra20 is
currently ths only version of tegra that instantiates an SFLASH
controller.This driver supports basic PIO mode of operation and is configurable
(CONFIG_OF_CONTROL) to be driven off devicetree bindings. Up to 4
devices per controller may be attached, although typically only a
single chip select line is exposed from tegra per controller so in
reality this is usually limited to 1.To enable this driver, use CONFIG_TEGRA_SLINK
Signed-off-by: Allen Martin
Signed-off-by: Tom Warren
15 Nov, 2012
1 commit
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This patch adds SPI driver for EXYNOS.
Signed-off-by: Simon Glass
Signed-off-by: Padmavathi Venna
Signed-off-by: Gabe Black
Signed-off-by: Rajeshwari Shinde
Signed-off-by: Hatim Ali
Acked-by: Mike Frysinger
Acked-by: Simon Glass
Tested-by: jy0922.shim@samsung.com
Signed-off-by: Minkyu Kang
20 Sep, 2012
1 commit
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This patch adds a driver for Freescale Colfire Queued SPI bus.
Coded to work with 8 bits per transfer to use with SPI flash.
CPOL, CPHA, and CS_ACTIVE_HIGH can be configured.Tested with MCF5270 which have 4 chip selects.
Activate by #define CONFIG_CF_QSPI in board config.
Signed-off-by: Richard Retanubun
08 Aug, 2012
1 commit
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The patch "spi: tegra2: rename tegra2_spi.* to tegra_spi.*"
(sha1: edffa63d3d6e76991998789f9fcbaa483731ca65)
renamed tegra2_spi.c to tegra_spi.cand the patch "Merge branch 'master' of git://git.denx.de/u-boot-microblaze"
(sha1: d978780b2e676c005460cd561f4f15b5220bdf49)has wrongly resolved confict.
This patch fix it.
Signed-off-by: Michal Simek
01 Aug, 2012
1 commit
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* 'master' of git://git.denx.de/u-boot-microblaze:
microblaze: Wire up SPI driver
spi: microblaze: Adds driver for Xilinx SPI controller
microblaze: intc: Clear interrupt code
microblaze: Call serial multi initialization
microblaze: Move __udelay implementation
microblaze: Remove extern from board.c
microblaze: Wire up dts configuration
fdt: Add board specific dts inclusion
microblaze: Move individual board linker scripts to common script in cpu tree.
microblaze: Add gpio.h
microblaze: Add missing undefs for UBI and UBIFS
microblaze: Expand and correct configuration comments
microblaze: Enable ubi support
microblaze: Avoid compile error on systems without cfi flash
microblaze: Remove wrong define CONFIG_SYS_FLASH_PROTECTIONConflicts:
drivers/spi/MakefileSigned-off-by: Wolfgang Denk
31 Jul, 2012
1 commit
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This is an improved version of the driver patch original
submitted by Graeme SmecherThe changes are:
- remove hard coded Xilinx BSP defines (XPAR_SPI_*) and
use CONFIG_SYS_SPI_BASE from config.h instead
- add extensive register struct definitions
- remove offset calculation for register access and
use the new register struct instead
- move default SPI controller configuration from
spi_setup_slave() to spi_claim_bus()
- add spi_set_speed()
- insert SPI controller deactivation in spi_release_bus()
- protect while loops in spi_xfer() with counter / timeouts
- support SPI mode flags: LSB_FIRST, CPHA, CPOL, LOOPCome from:
http://patchwork.ozlabs.org/patch/71797/Signed-off-by: Stephan Linz
Tested-by: Michal Simek
07 Jul, 2012
1 commit
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In anticipation of Tegra3 support, start removing/renaming
Tegra2-specific files. No functional changes (yet).
Also updated copyright to 2012.Signed-off-by: Tom Warren
24 Dec, 2011
1 commit
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This driver supports SPI on Tegra2, running at 48MHz.
Signed-off-by: Tom Warren
Acked-by: Mike Frysinger
11 Nov, 2011
1 commit
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Signed-off-by: Marek Vasut
Cc: Stefano Babic
Cc: Wolfgang Denk
Cc: Detlev Zundel
28 Oct, 2011
1 commit
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This patch provides support for SPI emulated over SSP for Marvell
Armada100 SOC.Signed-off-by: Ajay Bhargav
26 Jul, 2011
1 commit
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andes_spi is an spi interface developed by Andes Tech.
Signed-off-by: Macpaul Lin
Cc: Wolfgang Denk
Cc: Mike Frysinger
Acked-by: Mike Frysinger
01 May, 2011
2 commits
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This patch adds support for OpenCores tiny_spi.
http://opencores.org/project,tiny_spi
Signed-off-by: Thomas Chou
29 Apr, 2011
1 commit
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Signed-off-by: Mingkai Hu
Singed-off-by: Jerry Huang
Signed-off-by: Shaohui Xie
Cc: Mike Frysinger
Signed-off-by: Kumar Gala
02 Feb, 2011
1 commit
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SH7757 has SPI module. This patch supports it.
Signed-off-by: Yoshihiro Shimoda
Signed-off-by: Nobuhiro Iwamatsu
12 Dec, 2010
1 commit
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CC: Ruslan N. Araslanov
Signed-off-by: Ruslan Araslanov
Signed-off-by: Sandeep Paulraj
