26 Jan, 2010
1 commit
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Signed-off-by: Liu Yu
Signed-off-by: Kumar Gala
24 Jan, 2010
1 commit
23 Jan, 2010
8 commits
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Normally the processor clock has a divisor of 2.
In some cases this this needs to be set to 4.
Check the user has set environment mdiv to 4 to change the divisor.Signed-off-by: Daniel Gorsulowski
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SPEAr320 SoC support contains basic spear320 support along with the
usage of following drivers
- serial driver(UART)
- i2c driver
- smi driver
- nand driver(FSMC)
- usbd driver
- emi driver(cfi support)Signed-off-by: Vipin
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SPEAr310 SoC support contains basic spear310 support along with the
usage of following drivers
- serial driver(UART)
- i2c driver
- smi driver
- nand driver(FSMC)
- usbd driver
- emi driver(cfi support)Signed-off-by: Vipin
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SPEAr310 and SPEAr320 SoCs contain an EMI controller to interface
Paraller NOR flashes. This patch adds the support for this IPThe standard CFI driver is used to interface with NOR flashes
Signed-off-by: Vipin
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SPEAr300 SoC support contains basic spear300 support along with the
usage of following drivers
- serial driver(UART)
- i2c driver
- smi driver
- nand driver(FSMC)
- usbd driverSigned-off-by: Vipin
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This patch adds the support to read and write mac id from i2c
memory.
For reading:
if (env contains ethaddr)
pick env ethaddr
else
pick ethaddr from i2c memory
For writing:
chip_config ethaddr XX:XX:XX:XX:XX:XX writes the mac id
in i2c memorySigned-off-by: Vipin
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SPEAr600 SoC support contains basic spear600 support along with the
usage of following drivers
- serial driver(UART)
- i2c driver
- smi driver
- nand driver(FSMC)
- usbd driverSigned-off-by: Vipin
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A newer CPLD version on the 405EX evaluation board requires a different
EBC controller setup for the CPLD register access. This patch adds a CPLD
version detection for Kilauea and code to reconfigure the EBC controller
(chip select 2) for the old CPLD if no new version is found.Additionally the CPLD version is printed upon bootup:
Board: Kilauea - AMCC PPC405EX Evaluation Board (CPLD rev. 0)
Signed-off-by: Stefan Roese
Acked-by: Wolfgang Denk
Cc: Zhang Bao Quan
18 Jan, 2010
3 commits
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- malloc size 4 MB for all keymile boards
- use generic FDT code for fixing up the DTS
- enable unit-led at startup for keymile boards
- remove some dts updates for keymile boards
- ppc_83xx, kmeter1: take FE/GbE PHYs out of reset
- ppc_83xx, kmeter1: change from Intel Strata to Spansion 64MB flash
changed from Intel Strata to Spansion 64MB flash and changed flash layout.
+---------+----------+-----------------------+-----------------------------+
| name | size | range | description |
+---------+----------+-----------------------+-----------------------------+
| u-boot | 768 KB | 0xf0000000-0xf00bffff | for u-boot |
| env | 128 KB | 0xf00c0000-0xf00dffff | for environment |
| envred | 128 KB | 0xf00e0000-0xf00fffff | for environment (redundant) |
| ubi0 | 64512 KB | 0xf0100000-0xf3ffffff | ubi0 for ubi volumes |
+---------+----------+-----------------------+-----------------------------+Signed-off-by: Heiko Schocher
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When referring to PCIe and USB 'endpoint' is the standard naming
convention.Signed-off-by: Peter Tyser
Acked-by: Stefan Roese
Acked-by: Remy Bohmer
17 Jan, 2010
7 commits
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Signed-off-by: Harald Krapfenbauer
Signed-off-by: Mike Frysinger -
The new board revision has a different LCD.
Signed-off-by: Michael Hennerich
Signed-off-by: Mike Frysinger -
Signed-off-by: Cliff Cai
Signed-off-by: Mike Frysinger -
Give the CF/IDE code its own file to keep things cleanly separated. While
we're here, clean up the code to use common functions.Signed-off-by: Mike Frysinger
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Signed-off-by: Cliff Cai
Signed-off-by: Mike Frysinger -
While the initdram() function makes sense on some arches, it doesn't for
Blackfin systems as it's always implemented the same way.Signed-off-by: Mike Frysinger
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Signed-off-by: Valentin Yakovenkov
Signed-off-by: Mike Frysinger
13 Jan, 2010
3 commits
09 Jan, 2010
1 commit
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USB0_DRVVBUS pinmux configuration is required for USB functinality
in uboot.Signed-off-by: Ajay Kumar Gupta
Signed-off-by: Swaminathan S
08 Jan, 2010
3 commits
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Remove PCI reset, if there is a monarch PMC module.
Signed-off-by: Reinhard Arlt
Signed-off-by: Stefan Roeseconvert clrbits_be32 + setbits_be32 to clrsetbits_be32, use out_be32 to set gcr.
Signed-off-by: Kim Phillips
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The caddy2 is a variant of the already supported vme8349. So we just
add the differences to this board port. To better support those two
boards we switched from fixed SDRAM configuration to usage of
spd_sdram(). This is done by providing a board specific SPD EEPROM
routine with different values for both boards.Signed-off-by: Reinhard Arlt
Signed-off-by: Stefan Roesechanged to use mkconfig -t option instead, plus misc codingstyle fixes.
Signed-off-by: Kim Phillips
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The core support for NAND booting is there already, so this patch
is pretty straightforward.There is one trick though: top level Makefile expects nand_spl to
be in nand_spl/board/$(BOARDDIR), but we can fully reuse the code
from mpc8313erdb boards, and so to not duplicate the code we just
symlink nand_spl/board/freescale/mpc8315erdb to mpc8313erdb.Signed-off-by: Anton Vorontsov
o silence make during ln echo
o update documentation
o and avoid:$ ./MAKEALL MPC8315ERDB_NAND
Configuring for MPC8315ERDB board...
sdram.o: In function `fixed_sdram':
/home/r1aaha/git/u-boot/nand_spl/board/freescale/mpc8313erdb/sdram.c:72: undefined reference to `udelay'by renaming udelay -> __udelay in the spirit of commit
3eb90bad651fab39cffba750ec4421a9c01d60e7 "Generic udelay() with watchdog
support".Signed-off-by: Kim Phillips
06 Jan, 2010
13 commits
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Thanks to "Errata to MPC8569E PowerQUICC III Integrated Host Processor
Family Reference Manual, Rev. 0" document, which describes all eSDHC
pins, we can add 4-bits eSDHC support for MPC8569E-MDS boards.Signed-off-by: Anton Vorontsov
Signed-off-by: Kumar Gala -
We already map the page cache-inhibited. There is no reason we
shouldn't also be marking it guarded to prevent speculative accesses.Signed-off-by: Kumar Gala
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Rather than hard coding which TLB entry the FLASH is mapped with we can
use find_tlb_idx to determine the entry.Signed-off-by: Kumar Gala
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We can use fsl_setup_hose to determine if we are a agent/end-point or
a host. Rather than using some SoC specific register we can just look
at the PCI cfg space of the host controller to determine this.Signed-off-by: Kumar Gala
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We can use fsl_setup_hose to determine if we are a agent/end-point or
a host. Rather than using some SoC specific register we can just look
at the PCI cfg space of the host controller to determine this.Signed-off-by: Kumar Gala
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We can use fsl_setup_hose to determine if we are a agent/end-point or
a host. Rather than using some SoC specific register we can just look
at the PCI cfg space of the host controller to determine this.Signed-off-by: Kumar Gala
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We can use fsl_setup_hose to determine if we are a agent/end-point or
a host. Rather than using some SoC specific register we can just look
at the PCI cfg space of the host controller to determine this.Signed-off-by: Kumar Gala
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Use new fsl_pci_init_port() that reduces amount of duplicated code in the
board ports, use IO accessors and clean up printing of status info.Signed-off-by: Kumar Gala
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Use new fsl_pci_init_port() that reduces amount of duplicated code in the
board ports, use IO accessors and clean up printing of status info.Signed-off-by: Kumar Gala
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Use new fsl_pci_init_port() that reduces amount of duplicated code in the
board ports, use IO accessors and clean up printing of status info.Signed-off-by: Kumar Gala
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Use new fsl_pci_init_port() that reduces amount of duplicated code in the
board ports, use IO accessors and clean up printing of status info.Signed-off-by: Kumar Gala
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Use new fsl_pci_init_port() that reduces amount of duplicated code in the
board ports, use IO accessors and clean up printing of status info.Signed-off-by: Kumar Gala
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Use new fsl_pci_init_port() that reduces amount of duplicated code in the
board ports, use IO accessors and clean up printing of status info.Signed-off-by: Kumar Gala
