15 Feb, 2018
1 commit
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Upon further review, not all code authors are in favour of this change.
This reverts commit ee3556bcafbb05e59aabdc31368984e76acaabc4.Signed-off-by: Tom Rini
10 Feb, 2018
1 commit
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To make this driver easier to be reused, dual-license DDR driver.
Signed-off-by: York Sun
CC: Simon Glass
CC: Tom Rini
CC: Heinrich Schuchardt
CC: Thomas Schaefer
CC: Masahiro Yamada
CC: Robert P. J. Day
CC: Alexander Merkle
CC: Joakim Tjernlund
CC: Curt Brune
CC: Valentin Longchamp
CC: Wolfgang Denk
CC: Anatolij Gustschin
CC: Ira W. Snyder
CC: Marek Vasut
CC: Kyle Moffett
CC: Sebastien Carlier
CC: Stefan Roese
CC: Peter Tyser
CC: Paul Gortmaker
CC: Peter Tyser
CC: Jean-Christophe PLAGNIOL-VILLARD
05 Jan, 2017
1 commit
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These two macros are used for the same thing, the total number of DDR
controllers for a given SoC. Use SYS_NUM_DDR_CTRLS in Kconfig and
merge existing usage.Signed-off-by: York Sun
06 Dec, 2016
1 commit
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- add additional function erratum_a009942_check_cpo to check if the
board needs tuning CPO calibration for optimal setting.
- move ERRATUM_A009942(with revision to check cpo_sample option) from
fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts.
- move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c
- remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942.Signed-off-by: Shengzhou Liu
[YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500]
Reviewed-by: York Sun
19 Jan, 2016
1 commit
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In a number of places we had wordings of the GPL (or LGPL in a few
cases) license text that were split in such a way that it wasn't caught
previously. Convert all of these to the correct SPDX-License-Identifier
tag.Signed-off-by: Tom Rini
01 Dec, 2015
1 commit
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Freescale LSCH3 platforms use two DDR controlers interleaving mode out of
reset. It can be configured to disable one controller. To support this
operation, the driver needs to detect and skip the disabled controller.Signed-off-by: York Sun
04 Aug, 2015
1 commit
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By default the bstopre value has been set to 0x100, used to be 1/4
value of refint. Modern DDR has increased the refresh time. Adjust
to 1/4 of refresh interval dynamically. Individual board can still
override this value in board ddr file, or to use auto-precharge.Signed-off-by: York Sun
21 Jul, 2015
1 commit
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In case SPD address changes between board revisions, updating SPD
address can be called from board file.Signed-off-by: York Sun
Signed-off-by: Prabhakar Kushwaha
23 Apr, 2015
1 commit
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Add/update registers for DDR4, including DQ mappings. Allow raw timing
method used for all controllers. Update mode_9 register to 0x500 for
improved stability. Check DDR controller version number individually
in case a SoC has multiple DDR controllers of different versions.
Increase read-write turnaround for DDR4 high speeds.Signed-off-by: York Sun
25 Feb, 2015
2 commits
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Add sync of refresh for multiple DDR controllers. DDRC initialization
needs to complete first. Code is re-ordered to keep refresh close.Signed-off-by: York Sun
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Controller number is passed for function calls to support individual
DDR clock, depending on SoC implementation. It is backward compatible
with exising platforms. Multiple clocks have been verifyed on LS2085A
emulator.Signed-off-by: York Sun
24 Jan, 2015
1 commit
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Internal memory controller counters can reach a bad state after
training in DDR4 mode if accumulated ECC or DBI mode is eanbled.Signed-off-by: York Sun
25 Sep, 2014
1 commit
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U-boot has been initializing DDR for the main memory. The presumption
is the memory stays as a big continuous block, either linear or
interleaved. This change is to support putting some DDR controllers
to separated space without counting into main memory. The standalone
memory controller could use different number of DIMM slots.Signed-off-by: York Sun
23 Apr, 2014
1 commit
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Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register
calculation and programming.Signed-off-by: York Sun
22 Feb, 2014
1 commit
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Initially it was believed the DDR controller on Freescale ARM would have
big endian. But some platform will have little endian.Signed-off-by: York Sun
26 Nov, 2013
1 commit
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Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs.
The similar DDR controllers will be used for ARM-based SoCs.Signed-off-by: York Sun